| Message ID | 168149412855.4013891.16386221304030694671.stgit@djiang5-mobl3 |
|---|---|
| Headers | show |
| Series | ndctl: Add support of QoS Throttling Group (QTG) id for CXL CLI | expand |
On Fri, Apr 14, 2023 at 10:42:55AM -0700, Dave Jiang wrote: > The series adds support for the kernel enabling [1] of QoS Throttling Group > (QTG) id. The kernel exports a QTG id for the root decoders (CFMWS) and as > well as for the CXL memory devices. The QTG id exported for a device is > calculated by the driver during device probe. Currently a QTG id is exported > for the volatile partition and another for the persistent partition. In the > future QTG id(s) will be exported for DCD regions. Display of QTG id is > through the CXL CLI list command. > > A QTG id check as also been added for region creation. A warning is emitted > when the QTG id of a memory range of a CXL memory device being included in > the CXL region assembly does not match the QTG id of the root decoder. Options > are available to suppress the warning or to fail the region creation. This > enabling provides a guidance on flagging memory ranges being used is not > optimal for performance for the CXL region to be formed. Can you cut/paste me some cxl list sample output? I'm not going to be trying this out to review. Thanks! > > [1]: https://lore.kernel.org/linux-cxl/168088732996.1441063.10107817505475386072.stgit@djiang5-mobl3/T/#t > > --- > > Dave Jiang (3): > ndctl: Add QTG ID support for the root decoder > ndctl: Add QTG ID support for the memory device > ndctl: add QTG ID check for region creation > > > Documentation/cxl/cxl-create-region.txt | 9 ++++ > cxl/json.c | 22 +++++++++- > cxl/lib/libcxl.c | 31 ++++++++++++++ > cxl/lib/libcxl.sym | 3 ++ > cxl/lib/private.h | 3 ++ > cxl/libcxl.h | 5 +++ > cxl/region.c | 57 ++++++++++++++++++++++++- > 7 files changed, 128 insertions(+), 2 deletions(-) > > -- >
On 4/14/23 2:49 PM, Alison Schofield wrote: > On Fri, Apr 14, 2023 at 10:42:55AM -0700, Dave Jiang wrote: >> The series adds support for the kernel enabling [1] of QoS Throttling Group >> (QTG) id. The kernel exports a QTG id for the root decoders (CFMWS) and as >> well as for the CXL memory devices. The QTG id exported for a device is >> calculated by the driver during device probe. Currently a QTG id is exported >> for the volatile partition and another for the persistent partition. In the >> future QTG id(s) will be exported for DCD regions. Display of QTG id is >> through the CXL CLI list command. >> >> A QTG id check as also been added for region creation. A warning is emitted >> when the QTG id of a memory range of a CXL memory device being included in >> the CXL region assembly does not match the QTG id of the root decoder. Options >> are available to suppress the warning or to fail the region creation. This >> enabling provides a guidance on flagging memory ranges being used is not >> optimal for performance for the CXL region to be formed. > > Can you cut/paste me some cxl list sample output? I'm not going to be > trying this out to review. # cxl list -D [ { "decoder":"decoder0.0", "resource":49660559360, "size":4294967296, "interleave_ways":1, "max_available_extent":4294967296, "pmem_capable":true, "volatile_capable":true, "accelmem_capable":true, "qtg_id":0, "nr_targets":1 }, { "decoder":"decoder0.1", "resource":53955526656, "size":4294967296, "interleave_ways":2, "interleave_granularity":8192, "max_available_extent":4294967296, "pmem_capable":true, "volatile_capable":true, "accelmem_capable":true, "qtg_id":0, "nr_targets":2 } ] # cxl list [ { "memdev":"mem3", "ram_size":268435456, "qtg_id":0, "serial":0, "host":"0000:c5:00.0" }, { "memdev":"mem5", "pmem_size":268435456, "qtg_id":0, "serial":0, "host":"0000:c2:00.0" }, { "memdev":"mem2", "ram_size":268435456, "qtg_id":0, "serial":0, "host":"0000:c4:00.0" }, { "memdev":"mem7", "pmem_size":268435456, "qtg_id":0, "serial":0, "host":"0000:c3:00.0" }, { "memdev":"mem6", "ram_size":268435456, "qtg_id":0, "serial":0, "host":"0000:38:00.0" }, { "memdev":"mem1", "pmem_size":268435456, "qtg_id":0, "serial":0, "host":"0000:37:00.0" }, { "memdev":"mem4", "ram_size":268435456, "qtg_id":0, "serial":0, "host":"0000:39:00.0" }, { "memdev":"mem0", "pmem_size":268435456, "qtg_id":0, "serial":0, "host":"0000:36:00.0" } ] > > Thanks! > > >> >> [1]: https://lore.kernel.org/linux-cxl/168088732996.1441063.10107817505475386072.stgit@djiang5-mobl3/T/#t >> >> --- >> >> Dave Jiang (3): >> ndctl: Add QTG ID support for the root decoder >> ndctl: Add QTG ID support for the memory device >> ndctl: add QTG ID check for region creation >> >> >> Documentation/cxl/cxl-create-region.txt | 9 ++++ >> cxl/json.c | 22 +++++++++- >> cxl/lib/libcxl.c | 31 ++++++++++++++ >> cxl/lib/libcxl.sym | 3 ++ >> cxl/lib/private.h | 3 ++ >> cxl/libcxl.h | 5 +++ >> cxl/region.c | 57 ++++++++++++++++++++++++- >> 7 files changed, 128 insertions(+), 2 deletions(-) >> >> -- >>
On Fri, Apr 14, 2023 at 04:27:47PM -0700, Dave Jiang wrote: > > > On 4/14/23 2:49 PM, Alison Schofield wrote: > > On Fri, Apr 14, 2023 at 10:42:55AM -0700, Dave Jiang wrote: > > > The series adds support for the kernel enabling [1] of QoS Throttling Group > > > (QTG) id. The kernel exports a QTG id for the root decoders (CFMWS) and as > > > well as for the CXL memory devices. The QTG id exported for a device is > > > calculated by the driver during device probe. Currently a QTG id is exported > > > for the volatile partition and another for the persistent partition. In the > > > future QTG id(s) will be exported for DCD regions. Display of QTG id is > > > through the CXL CLI list command. > > > > > > A QTG id check as also been added for region creation. A warning is emitted > > > when the QTG id of a memory range of a CXL memory device being included in > > > the CXL region assembly does not match the QTG id of the root decoder. Options > > > are available to suppress the warning or to fail the region creation. This > > > enabling provides a guidance on flagging memory ranges being used is not > > > optimal for performance for the CXL region to be formed. > > > > Can you cut/paste me some cxl list sample output? I'm not going to be > > trying this out to review. Thanks for the samples. The cxl list man page sample output may need updating. Alison > # cxl list -D > [ > { > "decoder":"decoder0.0", > "resource":49660559360, > "size":4294967296, > "interleave_ways":1, > "max_available_extent":4294967296, > "pmem_capable":true, > "volatile_capable":true, > "accelmem_capable":true, > "qtg_id":0, > "nr_targets":1 > }, > { > "decoder":"decoder0.1", > "resource":53955526656, > "size":4294967296, > "interleave_ways":2, > "interleave_granularity":8192, > "max_available_extent":4294967296, > "pmem_capable":true, > "volatile_capable":true, > "accelmem_capable":true, > "qtg_id":0, > "nr_targets":2 > } > ] > > # cxl list > [ > { > "memdev":"mem3", > "ram_size":268435456, > "qtg_id":0, > "serial":0, > "host":"0000:c5:00.0" > }, > { > "memdev":"mem5", > "pmem_size":268435456, > "qtg_id":0, > "serial":0, > "host":"0000:c2:00.0" > }, > { > "memdev":"mem2", > "ram_size":268435456, > "qtg_id":0, > "serial":0, > "host":"0000:c4:00.0" > }, > { > "memdev":"mem7", > "pmem_size":268435456, > "qtg_id":0, > "serial":0, > "host":"0000:c3:00.0" > }, > { > "memdev":"mem6", > "ram_size":268435456, > "qtg_id":0, > "serial":0, > "host":"0000:38:00.0" > }, > { > "memdev":"mem1", > "pmem_size":268435456, > "qtg_id":0, > "serial":0, > "host":"0000:37:00.0" > }, > { > "memdev":"mem4", > "ram_size":268435456, > "qtg_id":0, > "serial":0, > "host":"0000:39:00.0" > }, > { > "memdev":"mem0", > "pmem_size":268435456, > "qtg_id":0, > "serial":0, > "host":"0000:36:00.0" > } > ] > > > > > > > Thanks! > > > > > > > > > > [1]: https://lore.kernel.org/linux-cxl/168088732996.1441063.10107817505475386072.stgit@djiang5-mobl3/T/#t > > > > > > --- > > > > > > Dave Jiang (3): > > > ndctl: Add QTG ID support for the root decoder > > > ndctl: Add QTG ID support for the memory device > > > ndctl: add QTG ID check for region creation > > > > > > > > > Documentation/cxl/cxl-create-region.txt | 9 ++++ > > > cxl/json.c | 22 +++++++++- > > > cxl/lib/libcxl.c | 31 ++++++++++++++ > > > cxl/lib/libcxl.sym | 3 ++ > > > cxl/lib/private.h | 3 ++ > > > cxl/libcxl.h | 5 +++ > > > cxl/region.c | 57 ++++++++++++++++++++++++- > > > 7 files changed, 128 insertions(+), 2 deletions(-) > > > > > > -- > > >
The series adds support for the kernel enabling [1] of QoS Throttling Group (QTG) id. The kernel exports a QTG id for the root decoders (CFMWS) and as well as for the CXL memory devices. The QTG id exported for a device is calculated by the driver during device probe. Currently a QTG id is exported for the volatile partition and another for the persistent partition. In the future QTG id(s) will be exported for DCD regions. Display of QTG id is through the CXL CLI list command. A QTG id check as also been added for region creation. A warning is emitted when the QTG id of a memory range of a CXL memory device being included in the CXL region assembly does not match the QTG id of the root decoder. Options are available to suppress the warning or to fail the region creation. This enabling provides a guidance on flagging memory ranges being used is not optimal for performance for the CXL region to be formed. [1]: https://lore.kernel.org/linux-cxl/168088732996.1441063.10107817505475386072.stgit@djiang5-mobl3/T/#t --- Dave Jiang (3): ndctl: Add QTG ID support for the root decoder ndctl: Add QTG ID support for the memory device ndctl: add QTG ID check for region creation Documentation/cxl/cxl-create-region.txt | 9 ++++ cxl/json.c | 22 +++++++++- cxl/lib/libcxl.c | 31 ++++++++++++++ cxl/lib/libcxl.sym | 3 ++ cxl/lib/private.h | 3 ++ cxl/libcxl.h | 5 +++ cxl/region.c | 57 ++++++++++++++++++++++++- 7 files changed, 128 insertions(+), 2 deletions(-) --