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[v2,0/5] cxl: DPA partition metadata is a mess...

Message ID 173753635014.3849855.17902348420186052714.stgit@dwillia2-xfh.jf.intel.com
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Series cxl: DPA partition metadata is a mess... | expand

Message

Dan Williams Jan. 22, 2025, 8:59 a.m. UTC
Changes since v1: [0]
- Stop requiring PMEM to be at partition-index 1, i.e. remove empty
  partitions. (Jonathan)
- Document the assumptions and implementation of
  {request,release}_skip() (Jonathan, Alejandro)
- Kill 'enum cxl_decoder_mode' to cleanup remainder of hard-coded
  expectations of a static PMEM partition always being present

[0]: http://lore.kernel.org/173709422664.753996.4091585899046900035.stgit@dwillia2-xfh.jf.intel.com

---

As noted in patch3, the pending efforts to add CXL Accelerator (type-2)
device [1], and Dynamic Capacity (DCD) support [2], tripped on the
no-longer-fit-for-purpose design in the CXL subsystem for tracking
device-physical-address (DPA) metadata.

In fact there was no design at all, just a couple of open-coded 'struct
resource' instances for 'ram' and 'pmem' and a pile of explicit code
referencing those resources directly.

See patch3 for more details on the specific problems that caused, and
patch4 for the eyesore reduction of making the DPA allocation algorithm
partition number agnostic.

The motivation with this effort is to make it easier to land the Type-2
and DCD series.

[1]: http://lore.kernel.org/20241230214445.27602-1-alejandro.lucero-palau@amd.com
[2]: http://lore.kernel.org/20241210-dcd-type2-upstream-v8-0-812852504400@intel.com

---

Dan Williams (5):
      cxl: Remove the CXL_DECODER_MIXED mistake
      cxl: Introduce to_{ram,pmem}_{res,perf}() helpers
      cxl: Introduce 'struct cxl_dpa_partition' and 'struct cxl_range_info'
      cxl: Make cxl_dpa_alloc() DPA partition number agnostic
      cxl: Kill enum cxl_decoder_mode


 drivers/cxl/core/cdat.c      |   74 +++++-----
 drivers/cxl/core/core.h      |    4 -
 drivers/cxl/core/hdm.c       |  310 +++++++++++++++++++++++++++++++-----------
 drivers/cxl/core/mbox.c      |   66 +++------
 drivers/cxl/core/memdev.c    |   43 ++----
 drivers/cxl/core/port.c      |   20 ++-
 drivers/cxl/core/region.c    |  138 ++++++++++---------
 drivers/cxl/cxl.h            |   40 +----
 drivers/cxl/cxlmem.h         |   94 +++++++++++--
 drivers/cxl/mem.c            |    2 
 drivers/cxl/pci.c            |    7 +
 tools/testing/cxl/test/cxl.c |   22 +--
 tools/testing/cxl/test/mem.c |    7 +
 13 files changed, 511 insertions(+), 316 deletions(-)

base-commit: fac04efc5c793dccbd07e2d59af9f90b7fc0dca4

Comments

Alejandro Lucero Palau Jan. 23, 2025, 5:23 p.m. UTC | #1
On 1/22/25 08:59, Dan Williams wrote:
> Changes since v1: [0]
> - Stop requiring PMEM to be at partition-index 1, i.e. remove empty
>    partitions. (Jonathan)
> - Document the assumptions and implementation of
>    {request,release}_skip() (Jonathan, Alejandro)
> - Kill 'enum cxl_decoder_mode' to cleanup remainder of hard-coded
>    expectations of a static PMEM partition always being present
>
> [0]: http://lore.kernel.org/173709422664.753996.4091585899046900035.stgit@dwillia2-xfh.jf.intel.com
>
> ---
>
> As noted in patch3, the pending efforts to add CXL Accelerator (type-2)
> device [1], and Dynamic Capacity (DCD) support [2], tripped on the
> no-longer-fit-for-purpose design in the CXL subsystem for tracking
> device-physical-address (DPA) metadata.
>
> In fact there was no design at all, just a couple of open-coded 'struct
> resource' instances for 'ram' and 'pmem' and a pile of explicit code
> referencing those resources directly.
>
> See patch3 for more details on the specific problems that caused, and
> patch4 for the eyesore reduction of making the DPA allocation algorithm
> partition number agnostic.
>
> The motivation with this effort is to make it easier to land the Type-2
> and DCD series.
>
> [1]: http://lore.kernel.org/20241230214445.27602-1-alejandro.lucero-palau@amd.com
> [2]: http://lore.kernel.org/20241210-dcd-type2-upstream-v8-0-812852504400@intel.com
>
> ---
>
> Dan Williams (5):
>        cxl: Remove the CXL_DECODER_MIXED mistake
>        cxl: Introduce to_{ram,pmem}_{res,perf}() helpers
>        cxl: Introduce 'struct cxl_dpa_partition' and 'struct cxl_range_info'
>        cxl: Make cxl_dpa_alloc() DPA partition number agnostic
>        cxl: Kill enum cxl_decoder_mode
>

FWIW, I'll adapt the current CXL patchset as in v9 for testing the 
changes in this patchset and report here in the next days.


Thank you


>   drivers/cxl/core/cdat.c      |   74 +++++-----
>   drivers/cxl/core/core.h      |    4 -
>   drivers/cxl/core/hdm.c       |  310 +++++++++++++++++++++++++++++++-----------
>   drivers/cxl/core/mbox.c      |   66 +++------
>   drivers/cxl/core/memdev.c    |   43 ++----
>   drivers/cxl/core/port.c      |   20 ++-
>   drivers/cxl/core/region.c    |  138 ++++++++++---------
>   drivers/cxl/cxl.h            |   40 +----
>   drivers/cxl/cxlmem.h         |   94 +++++++++++--
>   drivers/cxl/mem.c            |    2
>   drivers/cxl/pci.c            |    7 +
>   tools/testing/cxl/test/cxl.c |   22 +--
>   tools/testing/cxl/test/mem.c |    7 +
>   13 files changed, 511 insertions(+), 316 deletions(-)
>
> base-commit: fac04efc5c793dccbd07e2d59af9f90b7fc0dca4