From patchwork Mon Mar 27 17:02:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Cameron X-Patchwork-Id: 13189720 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E4133C76195 for ; Mon, 27 Mar 2023 17:04:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232798AbjC0REe (ORCPT ); Mon, 27 Mar 2023 13:04:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52356 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232590AbjC0RDx (ORCPT ); Mon, 27 Mar 2023 13:03:53 -0400 Received: from frasgout.his.huawei.com (frasgout.his.huawei.com [185.176.79.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0C14D10D4; Mon, 27 Mar 2023 10:02:55 -0700 (PDT) Received: from lhrpeml500005.china.huawei.com (unknown [172.18.147.200]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4PlfHc6mgPz6J83R; Tue, 28 Mar 2023 01:02:04 +0800 (CST) Received: from SecurePC-101-06.china.huawei.com (10.122.247.231) by lhrpeml500005.china.huawei.com (7.191.163.240) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Mon, 27 Mar 2023 18:02:39 +0100 From: Jonathan Cameron To: Liang Kan , , CC: , , , , , , , , Davidlohr Bueso , Dave Jiang Subject: [PATCH v3 0/5] CXL 3.0 Performance Monitoring Unit support Date: Mon, 27 Mar 2023 18:02:42 +0100 Message-ID: <20230327170247.6968-1-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.37.2 MIME-Version: 1.0 X-Originating-IP: [10.122.247.231] X-ClientProxiedBy: lhrpeml500003.china.huawei.com (7.191.162.67) To lhrpeml500005.china.huawei.com (7.191.163.240) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org v3: Build fixes. Called out in individual patches. Reported-by: kernel test robot Link: https://lore.kernel.org/oe-kbuild-all/202303250419.FANh4fIC-lkp@intel.com/ Link: https://lore.kernel.org/oe-kbuild-all/202303250523.JdddC4Ld-lkp@intel.com/ Link: https://lore.kernel.org/oe-kbuild-all/202303250546.ijiFKIpM-lkp@intel.com/ etc Thanks to all those who have looked at v1, and Kan Liang in particular for all the feedback on the main driver. Updated cover letter. The CXL rev 3.0 specification introduces a CXL Performance Monitoring Unit definition. CXL components may have any number of these blocks. The definition is highly flexible, but that does bring complexity in the driver. Notes. 1) The QEMU model against which this was developed needs tidying up. Latest tree at https://gitlab.com/jic23/qemu branch cxl-2023-02-28 It's backed up behind other series that I plan to upstream first. 2) There are quite a lot of corner cases that will need working through with variants of the model, or I'll have to design a pathological set of CPMUs to hit all the corner cases in one go. So whilst I believe the driver should be fine for what it supports we may find issues as those corners of what is allowed are explored. 3) I'm not sure it makes sense to hang this of the cxl/pci driver but couldn't really figure out where else in the current structure we could make it fit cleanly. 4) Driver location. In past perf maintainers have requested perf drivers for PCI etc be under drivers/perf. That would require moving some CXL headers to be more generally visible, but is certainly possible if there is agreement between CXL and perf maintainers on the correct location. 5) Patch 1 led to a discussion of how to handle the self describing and extensible nature of the CPMU counters. That is likely to involve a description in the "caps" sysfs directory and perf tool code that is aware of the different event combinations that make sense and can establish which sets are available on a given device. That is likely to take a while to converge on, so as the driver is useful in the current state, I'm looking to upstream this first and deal with the more complex handling later. 6) There is a lot of other functionality that can be added in future include allowing for simpler hardware implementations that may not support the minimum level of features currently required by the driver (freeze, overflow interrupts etc). CXL rev 3.0 specification available from https://www.computeexpresslink.org Jonathan Cameron (5): cxl: Add function to count regblocks of a given type perf: Allow a PMU to have a parent cxl/pci: Find and register CXL PMU devices cxl: CXL Performance Monitoring Unit driver docs: perf: Minimal introduction the the CXL PMU device and driver Documentation/admin-guide/perf/cxl.rst | 65 ++ Documentation/admin-guide/perf/index.rst | 1 + drivers/cxl/Kconfig | 13 + drivers/cxl/Makefile | 1 + drivers/cxl/core/Makefile | 1 + drivers/cxl/core/core.h | 1 + drivers/cxl/core/cpmu.c | 72 ++ drivers/cxl/core/pci.c | 2 +- drivers/cxl/core/port.c | 4 +- drivers/cxl/core/regs.c | 50 +- drivers/cxl/cpmu.c | 939 +++++++++++++++++++++++ drivers/cxl/cpmu.h | 56 ++ drivers/cxl/cxl.h | 17 +- drivers/cxl/cxlpci.h | 1 + drivers/cxl/pci.c | 27 +- include/linux/perf_event.h | 1 + kernel/events/core.c | 1 + 17 files changed, 1244 insertions(+), 8 deletions(-) create mode 100644 Documentation/admin-guide/perf/cxl.rst create mode 100644 drivers/cxl/core/cpmu.c create mode 100644 drivers/cxl/cpmu.c create mode 100644 drivers/cxl/cpmu.h