[v5,0/5] hw/cxl: Line length reduction and related

Message

Jonathan Cameron Oct. 23, 2023, 2:02 p.m. UTC

v5:
 - As _Static_assert() is a declaration it cannot follow a label (until
   C23).
   Upshot of that is to compile in clang (possibly older GCC) we need
   to add {} to case statements that start with QEMU_BUILD_BUG_ON()
 - Add patch to handle another QEMU_BUILD_BUG_ON() case by dropping the
   unnecessary check.

Suggested-by: Michael S. Tsirkin <[e-mail]>

Michael observed that the CXL code regularly went above the 80 character
recommendation and in many cases this was not necessary for readability.

This series is focused on tidying this up for the existing code so that
we can maintain the preferred formatting going forwards.

Jonathan Cameron (5):
  hw/cxl: Use a switch to explicitly check size in caps_reg_read()
  hw/cxl: Use switch statements for read and write of cachemem registers
  hw/cxl: CXLDVSECPortExtensions renamed to CXLDVSECPortExt
  hw/cxl: Line length reductions
  hw/cxl: Fix a QEMU_BUILD_BUG_ON() in switch statement scope issue.

 include/hw/cxl/cxl_component.h |   3 +-
 include/hw/cxl/cxl_device.h    |   5 +-
 include/hw/cxl/cxl_events.h    |   3 +-
 include/hw/cxl/cxl_pci.h       |   6 +-
 hw/cxl/cxl-cdat.c              |   3 +-
 hw/cxl/cxl-component-utils.c   | 130 ++++++++++++++++++++-------------
 hw/cxl/cxl-device-utils.c      |  11 ++-
 hw/cxl/cxl-events.c            |   9 ++-
 hw/cxl/cxl-mailbox-utils.c     |  21 ++++--
 hw/mem/cxl_type3.c             |  31 +++++---
 hw/mem/cxl_type3_stubs.c       |   5 +-
 hw/pci-bridge/cxl_downstream.c |   2 +-
 hw/pci-bridge/cxl_root_port.c  |   2 +-
 hw/pci-bridge/cxl_upstream.c   |   2 +-
 14 files changed, 144 insertions(+), 89 deletions(-)