Message ID | 20240325235914.1897647-1-dave.jiang@intel.com |
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Headers | show
Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B205084D2A; Mon, 25 Mar 2024 23:59:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711411156; cv=none; b=pVcHTNSqb3VBrf8t6E0NQgreIMKYcUndtea/W3Yy3qY7nhCeXDoSXpBWlfHlEe3MK41h91Y42gOraDsz2FZCkEhSvmmWPddXbybnl1FmESHe1qoSTdNJOd1MYLBJ8H1MmgoyEE/d5QU092tNlTHJWKLeYxuWz0zxYBkavUZpM8o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711411156; c=relaxed/simple; bh=H+Z6duRuHTRQuL6SK2IWat0yxvpiuUkeq3z5doKshAA=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=VpxKk7VlvaH98hp1oto9mQGjfM3a3KC6lpbR3TmFPxcl68CPJIfDxWFfFhk44U4Kzvby6armvz/NVQ+onDijJU2H+YsxljYDcVTjRoAnRKkHZPugxm42lo0kmWJL5dvYKZmJO8TJRCQDGlb5AohK8llzFMcVyML1RYICXK3t6pw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6C535C433F1; Mon, 25 Mar 2024 23:59:16 +0000 (UTC) From: Dave Jiang <dave.jiang@intel.com> To: linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org Cc: dan.j.williams@intel.com, ira.weiny@intel.com, vishal.l.verma@intel.com, alison.schofield@intel.com, Jonathan.Cameron@huawei.com, dave@stgolabs.net, bhelgaas@google.com, lukas@wunner.de Subject: [PATCH 0/3 v2] PCI: Add Secondary Bus Reset (SBR) support for CXL Date: Mon, 25 Mar 2024 16:58:00 -0700 Message-ID: <20240325235914.1897647-1-dave.jiang@intel.com> X-Mailer: git-send-email 2.44.0 Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: <linux-cxl.vger.kernel.org> List-Subscribe: <mailto:linux-cxl+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-cxl+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit |
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PCI: Add Secondary Bus Reset (SBR) support for CXL
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