mbox series

[v9,0/2] check interleave capability

Message ID 20240614084755.59503-1-yaoxt.fnst@fujitsu.com
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Series check interleave capability | expand

Message

Xingtao Yao (Fujitsu) June 14, 2024, 8:47 a.m. UTC 
Currently, the cxl driver does not check the interleave capability of
devices (such as host bridges, switches, cxl_mem, etc.) when creating
a region.

When the driver adds a device to the region and sets its decoder, if the
device does not support the specified interleave ways or interleave
granularity, the device may ignore unsupported bits, causing the
configured decoder to be inconsistent with expectations.

During memory access, the decoder may decode the HPA into an incorrect DPA,
ultimately leading to memory access failure.

Checking the interleave capability of a device early in the process of
adding it to a region can quickly prevent this issue from occurring.

Changes:
V8[8] -> V9:
-- merge cxl_test modification into patch1.
-- append other missing files to kernel-doc and fix the complie warning.
-- optimize the interleave capability check logical.

V7[7] -> V8:
-- drop the redundant check in check_interleave_cap().
-- add cxlmem.h to kernel-doc. (newly add)
-- fixup cxl_test. (newly add)

V6[6] -> V7:
-- update comment.

V5[5] -> V6:
-- fix some typo.
-- update comment.
-- set rc when check failed in cxl_port_attach_region().

V4[4] -> V5:
-- update comment.
-- add nr_targets check while attaching a port to switch.
-- delete passthrough flag and allow all the capabilities for passthrough
   decoders.

V3[3] -> V4:
-- update comment.
-- optimize the code.
-- add a passthrough flag to mark the passthrough decoder.

V2[2] -> V3:
-- revert ig_cap_mask to interleave_mask.
-- fix the interleave bits check logical.

V1[1] -> V2:
-- rename interleave_mask to ig_cap_mask.
-- add a check for interleave granularity.
-- update commit.
-- move hdm caps init to parse_hdm_decoder_caps().

[1]
https://lore.kernel.org/linux-cxl/20240401075635.9333-1-yaoxt.fnst@fujitsu.com

[2]
https://lore.kernel.org/linux-cxl/20240403021747.17260-1-yaoxt.fnst@fujitsu.com

[3]
https://lore.kernel.org/linux-cxl/20240409022621.29115-1-yaoxt.fnst@fujitsu.com

[4]
https://lore.kernel.org/linux-cxl/20240422091350.4701-1-yaoxt.fnst@fujitsu.com

[5]
https://lore.kernel.org/linux-cxl/20240524092740.4260-1-yaoxt.fnst@fujitsu.com

[6]
https://lore.kernel.org/linux-cxl/20240611021511.35315-1-yaoxt.fnst@fujitsu.com

[7]
https://lore.kernel.org/linux-cxl/20240612032544.39149-1-yaoxt.fnst@fujitsu.com

[8]
https://lore.kernel.org/linux-cxl/20240614032133.45365-1-yaoxt.fnst@fujitsu.com

Yao Xingtao (2):
  cxl/region: check interleave capability
  cxl: documentation: add missing files to cxl driver-api

 .../driver-api/cxl/memory-devices.rst         | 15 ++++
 drivers/cxl/core/hdm.c                        | 13 +++
 drivers/cxl/core/region.c                     | 82 +++++++++++++++++++
 drivers/cxl/cxl.h                             |  2 +
 drivers/cxl/cxlmem.h                          | 21 +++--
 tools/testing/cxl/test/cxl.c                  |  4 +
 6 files changed, 132 insertions(+), 5 deletions(-)