diff mbox series

[5/5] cxl/hdm: Add more HDM decoder debug messages at startup

Message ID 168149845668.792294.11814353796371419167.stgit@dwillia2-xfh.jf.intel.com
State Accepted
Commit c841ecd8277154c9297dd9ac959494f6deb61e76
Headers show
Series cxl/hdm: Decoder enumeration fixes | expand

Commit Message

Dan Williams April 14, 2023, 6:54 p.m. UTC 
A recent debug session yielded a couple debug messages that were useful
for determining the reason why the driver was or was not falling back
to CXL range register emulation, and for identifying decoder setting
enumeration problems.

Signed-off-by: Dan Williams <dan.j.williams@intel.com>
---
 drivers/cxl/core/hdm.c |   12 ++++++++++++
 1 file changed, 12 insertions(+)

Comments

Alison Schofield April 14, 2023, 9:06 p.m. UTC | #1 
On Fri, Apr 14, 2023 at 11:54:16AM -0700, Dan Williams wrote:
> A recent debug session yielded a couple debug messages that were useful
> for determining the reason why the driver was or was not falling back
> to CXL range register emulation, and for identifying decoder setting
> enumeration problems.
> 
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>

Reviewed-by: Alison Schofield <alison.schofield@intel.com>

> ---
>  drivers/cxl/core/hdm.c |   12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
> index abe3877cfa63..7889ff203a34 100644
> --- a/drivers/cxl/core/hdm.c
> +++ b/drivers/cxl/core/hdm.c
> @@ -130,6 +130,14 @@ static bool should_emulate_decoders(struct cxl_endpoint_dvsec_info *info)
>  	 */
>  	for (i = 0; i < cxlhdm->decoder_count; i++) {
>  		ctrl = readl(hdm + CXL_HDM_DECODER0_CTRL_OFFSET(i));
> +		dev_dbg(&info->port->dev,
> +			"decoder%d.%d: committed: %ld base: %#x_%.8x size: %#x_%.8x\n",
> +			info->port->id, i,
> +			FIELD_GET(CXL_HDM_DECODER0_CTRL_COMMITTED, ctrl),
> +			readl(hdm + CXL_HDM_DECODER0_BASE_HIGH_OFFSET(i)),
> +			readl(hdm + CXL_HDM_DECODER0_BASE_LOW_OFFSET(i)),
> +			readl(hdm + CXL_HDM_DECODER0_SIZE_HIGH_OFFSET(i)),
> +			readl(hdm + CXL_HDM_DECODER0_SIZE_LOW_OFFSET(i)));
>  		if (FIELD_GET(CXL_HDM_DECODER0_CTRL_COMMITTED, ctrl))
>  			return false;
>  	}
> @@ -868,6 +876,10 @@ static int init_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld,
>  	if (rc)
>  		return rc;
>  
> +	dev_dbg(&port->dev, "decoder%d.%d: range: %#llx-%#llx iw: %d ig: %d\n",
> +		port->id, cxld->id, cxld->hpa_range.start, cxld->hpa_range.end,
> +		cxld->interleave_ways, cxld->interleave_granularity);
> +
>  	if (!info) {
>  		lo = readl(hdm + CXL_HDM_DECODER0_TL_LOW(which));
>  		hi = readl(hdm + CXL_HDM_DECODER0_TL_HIGH(which));
>
Dave Jiang April 14, 2023, 9:25 p.m. UTC | #2 
On 4/14/23 11:54 AM, Dan Williams wrote:
> A recent debug session yielded a couple debug messages that were useful
> for determining the reason why the driver was or was not falling back
> to CXL range register emulation, and for identifying decoder setting
> enumeration problems.
> 
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>

Reviewed-by: Dave Jiang <dave.jiang@intel.com>

> ---
>   drivers/cxl/core/hdm.c |   12 ++++++++++++
>   1 file changed, 12 insertions(+)
> 
> diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
> index abe3877cfa63..7889ff203a34 100644
> --- a/drivers/cxl/core/hdm.c
> +++ b/drivers/cxl/core/hdm.c
> @@ -130,6 +130,14 @@ static bool should_emulate_decoders(struct cxl_endpoint_dvsec_info *info)
>   	 */
>   	for (i = 0; i < cxlhdm->decoder_count; i++) {
>   		ctrl = readl(hdm + CXL_HDM_DECODER0_CTRL_OFFSET(i));
> +		dev_dbg(&info->port->dev,
> +			"decoder%d.%d: committed: %ld base: %#x_%.8x size: %#x_%.8x\n",
> +			info->port->id, i,
> +			FIELD_GET(CXL_HDM_DECODER0_CTRL_COMMITTED, ctrl),
> +			readl(hdm + CXL_HDM_DECODER0_BASE_HIGH_OFFSET(i)),
> +			readl(hdm + CXL_HDM_DECODER0_BASE_LOW_OFFSET(i)),
> +			readl(hdm + CXL_HDM_DECODER0_SIZE_HIGH_OFFSET(i)),
> +			readl(hdm + CXL_HDM_DECODER0_SIZE_LOW_OFFSET(i)));
>   		if (FIELD_GET(CXL_HDM_DECODER0_CTRL_COMMITTED, ctrl))
>   			return false;
>   	}
> @@ -868,6 +876,10 @@ static int init_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld,
>   	if (rc)
>   		return rc;
>   
> +	dev_dbg(&port->dev, "decoder%d.%d: range: %#llx-%#llx iw: %d ig: %d\n",
> +		port->id, cxld->id, cxld->hpa_range.start, cxld->hpa_range.end,
> +		cxld->interleave_ways, cxld->interleave_granularity);
> +
>   	if (!info) {
>   		lo = readl(hdm + CXL_HDM_DECODER0_TL_LOW(which));
>   		hi = readl(hdm + CXL_HDM_DECODER0_TL_HIGH(which));
>
Jonathan Cameron May 15, 2023, 10:52 a.m. UTC | #3 
On Fri, 14 Apr 2023 11:54:16 -0700
Dan Williams <dan.j.williams@intel.com> wrote:

> A recent debug session yielded a couple debug messages that were useful
> for determining the reason why the driver was or was not falling back
> to CXL range register emulation, and for identifying decoder setting
> enumeration problems.
> 
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
FWIW makes sense.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
>  drivers/cxl/core/hdm.c |   12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
> index abe3877cfa63..7889ff203a34 100644
> --- a/drivers/cxl/core/hdm.c
> +++ b/drivers/cxl/core/hdm.c
> @@ -130,6 +130,14 @@ static bool should_emulate_decoders(struct cxl_endpoint_dvsec_info *info)
>  	 */
>  	for (i = 0; i < cxlhdm->decoder_count; i++) {
>  		ctrl = readl(hdm + CXL_HDM_DECODER0_CTRL_OFFSET(i));
> +		dev_dbg(&info->port->dev,
> +			"decoder%d.%d: committed: %ld base: %#x_%.8x size: %#x_%.8x\n",
> +			info->port->id, i,
> +			FIELD_GET(CXL_HDM_DECODER0_CTRL_COMMITTED, ctrl),
> +			readl(hdm + CXL_HDM_DECODER0_BASE_HIGH_OFFSET(i)),
> +			readl(hdm + CXL_HDM_DECODER0_BASE_LOW_OFFSET(i)),
> +			readl(hdm + CXL_HDM_DECODER0_SIZE_HIGH_OFFSET(i)),
> +			readl(hdm + CXL_HDM_DECODER0_SIZE_LOW_OFFSET(i)));
>  		if (FIELD_GET(CXL_HDM_DECODER0_CTRL_COMMITTED, ctrl))
>  			return false;
>  	}
> @@ -868,6 +876,10 @@ static int init_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld,
>  	if (rc)
>  		return rc;
>  
> +	dev_dbg(&port->dev, "decoder%d.%d: range: %#llx-%#llx iw: %d ig: %d\n",
> +		port->id, cxld->id, cxld->hpa_range.start, cxld->hpa_range.end,
> +		cxld->interleave_ways, cxld->interleave_granularity);
> +
>  	if (!info) {
>  		lo = readl(hdm + CXL_HDM_DECODER0_TL_LOW(which));
>  		hi = readl(hdm + CXL_HDM_DECODER0_TL_HIGH(which));
>
diff mbox series

Patch

diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
index abe3877cfa63..7889ff203a34 100644
--- a/drivers/cxl/core/hdm.c
+++ b/drivers/cxl/core/hdm.c
@@ -130,6 +130,14 @@  static bool should_emulate_decoders(struct cxl_endpoint_dvsec_info *info)
 	 */
 	for (i = 0; i < cxlhdm->decoder_count; i++) {
 		ctrl = readl(hdm + CXL_HDM_DECODER0_CTRL_OFFSET(i));
+		dev_dbg(&info->port->dev,
+			"decoder%d.%d: committed: %ld base: %#x_%.8x size: %#x_%.8x\n",
+			info->port->id, i,
+			FIELD_GET(CXL_HDM_DECODER0_CTRL_COMMITTED, ctrl),
+			readl(hdm + CXL_HDM_DECODER0_BASE_HIGH_OFFSET(i)),
+			readl(hdm + CXL_HDM_DECODER0_BASE_LOW_OFFSET(i)),
+			readl(hdm + CXL_HDM_DECODER0_SIZE_HIGH_OFFSET(i)),
+			readl(hdm + CXL_HDM_DECODER0_SIZE_LOW_OFFSET(i)));
 		if (FIELD_GET(CXL_HDM_DECODER0_CTRL_COMMITTED, ctrl))
 			return false;
 	}
@@ -868,6 +876,10 @@  static int init_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld,
 	if (rc)
 		return rc;
 
+	dev_dbg(&port->dev, "decoder%d.%d: range: %#llx-%#llx iw: %d ig: %d\n",
+		port->id, cxld->id, cxld->hpa_range.start, cxld->hpa_range.end,
+		cxld->interleave_ways, cxld->interleave_granularity);
+
 	if (!info) {
 		lo = readl(hdm + CXL_HDM_DECODER0_TL_LOW(which));
 		hi = readl(hdm + CXL_HDM_DECODER0_TL_HIGH(which));