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[v6,37/43] tests/acpi: q35: Allow addition of a CXL test.

Message ID	20220211120747.3074-38-Jonathan.Cameron@huawei.com
State	Superseded
Headers	show Return-Path: <linux-cxl-owner@kernel.org> From: Jonathan Cameron <Jonathan.Cameron@huawei.com> To: <qemu-devel@nongnu.org>, =?utf-8?q?Alex_Benn=C3=A9e?= <alex.bennee@linaro.org>, Marcel Apfelbaum <marcel@redhat.com>, "Michael S . Tsirkin" <mst@redhat.com>, Igor Mammedov <imammedo@redhat.com> CC: <linux-cxl@vger.kernel.org>, Ben Widawsky <ben.widawsky@intel.com>, "Peter Maydell" <peter.maydell@linaro.org>, <linuxarm@huawei.com>, "Shameerali Kolothum Thodi" <shameerali.kolothum.thodi@huawei.com>, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <f4bug@amsat.org>, Saransh Gupta1 <saransh@ibm.com>, Shreyas Shah <shreyas.shah@elastics.cloud>, Chris Browy <cbrowy@avery-design.com>, Samarth Saxena <samarths@cadence.com>, "Dan Williams" <dan.j.williams@intel.com> Subject: [PATCH v6 37/43] tests/acpi: q35: Allow addition of a CXL test. Date: Fri, 11 Feb 2022 12:07:41 +0000 Message-ID: <20220211120747.3074-38-Jonathan.Cameron@huawei.com> In-Reply-To: <20220211120747.3074-1-Jonathan.Cameron@huawei.com> References: <20220211120747.3074-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7BIT Content-Type: text/plain; charset=US-ASCII Precedence: bulk
Series	CXl 2.0 emulation Support \| expand [v6,00/43] CXl 2.0 emulation Support [v6,01/43] hw/pci/cxl: Add a CXL component type (interface) [v6,02/43] hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5) [v6,03/43] MAINTAINERS: Add entry for Compute Express Link Emulation [v6,04/43] hw/cxl/device: Introduce a CXL device (8.2.8) [v6,05/43] hw/cxl/device: Implement the CAP array (8.2.8.1-2) [v6,06/43] hw/cxl/device: Implement basic mailbox (8.2.8.4) [v6,07/43] hw/cxl/device: Add memory device utilities [v6,08/43] hw/cxl/device: Add cheap EVENTS implementation (8.2.9.1) [v6,09/43] hw/cxl/device: Timestamp implementation (8.2.9.3) [v6,10/43] hw/cxl/device: Add log commands (8.2.9.4) + CEL [v6,11/43] hw/pxb: Use a type for realizing expanders [v6,12/43] hw/pci/cxl: Create a CXL bus type [v6,13/43] cxl: Machine level control on whether CXL support is enabled [v6,14/43] hw/pxb: Allow creation of a CXL PXB (host bridge) [v6,15/43] qtest/cxl: Introduce initial test for pxb-cxl only. [v6,16/43] hw/cxl/rp: Add a root port [v6,17/43] hw/cxl/device: Add a memory device (8.2.8.5) [v6,18/43] qtests/cxl: Add initial root port and CXL type3 tests [v6,19/43] hw/cxl/device: Implement MMIO HDM decoding (8.2.5.12) [v6,20/43] hw/cxl/device: Add some trivial commands [v6,21/43] hw/cxl/device: Plumb real Label Storage Area (LSA) sizing [v6,22/43] hw/cxl/device: Implement get/set Label Storage Area (LSA) [v6,23/43] hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142) [v6,24/43] acpi/cxl: Add _OSC implementation (9.14.2) [v6,25/43] acpi/cxl: Create the CEDT (9.14.1) [v6,26/43] hw/cxl/component: Add utils for interleave parameter encoding/decoding [v6,27/43] hw/cxl/host: Add support for CXL Fixed Memory Windows. [v6,28/43] acpi/cxl: Introduce CFMWS structures in CEDT [v6,29/43] hw/pci-host/gpex-acpi: Add support for dsdt construction for pxb-cxl [v6,30/43] pci/pcie_port: Add pci_find_port_by_pn() [v6,31/43] CXL/cxl_component: Add cxl_get_hb_cstate() [v6,32/43] mem/cxl_type3: Add read and write functions for associated hostmem. [v6,33/43] cxl/cxl-host: Add memops for CFMWS region. [v6,34/43] RFC: softmmu/memory: Add ops to memory_region_ram_init_from_file [v6,35/43] hw/cxl/component Add a dumb HDM decoder handler [v6,36/43] i386/pc: Enable CXL fixed memory windows [v6,37/43] tests/acpi: q35: Allow addition of a CXL test. [v6,38/43] qtests/bios-tables-test: Add a test for CXL emulation. [v6,39/43] tests/acpi: Add tables for CXL emulation. [v6,40/43] qtest/cxl: Add more complex test cases with CFMWs [v6,41/43] hw/arm/virt: Basic CXL enablement on pci_expander_bridge instances pxb-cxl [v6,42/43] qtest/cxl: Add aarch64 virt test for CXL [v6,43/43] docs/cxl: Add initial Compute eXpress Link (CXL) documentation.

Commit Message

Jonathan Cameron Feb. 11, 2022, 12:07 p.m. UTC

Add exceptions for the DSDT and the new CEDT tables
specific to a new CXL test in the following patch.

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 tests/data/acpi/q35/CEDT.cxl                | 0
 tests/data/acpi/q35/DSDT.cxl                | 0
 tests/qtest/bios-tables-test-allowed-diff.h | 2 ++
 3 files changed, 2 insertions(+)

diff mbox series

Patch

diff --git a/tests/data/acpi/q35/CEDT.cxl b/tests/data/acpi/q35/CEDT.cxl
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/tests/data/acpi/q35/DSDT.cxl b/tests/data/acpi/q35/DSDT.cxl
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..7c7f9fbc44 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,3 @@ 
 /* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/q35/DSDT.cxl",
+"tests/data/acpi/q35/CEDT.cxl",