From patchwork Wed Aug 24 23:24:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ira Weiny X-Patchwork-Id: 12954089 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA028C04AA5 for ; Wed, 24 Aug 2022 23:25:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231335AbiHXXY7 (ORCPT ); Wed, 24 Aug 2022 19:24:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38548 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231289AbiHXXY5 (ORCPT ); Wed, 24 Aug 2022 19:24:57 -0400 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2F01427B0F; Wed, 24 Aug 2022 16:24:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1661383496; x=1692919496; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3ajrhKAlyLex9P+GmLBl7RTGdiFSwUZrPHfyulLogHQ=; b=Xw2CDCdwxJMuFn4W+WNAkx+pvRylI4f84WzXc429KDv3lKWvzRVd88Tt +QgPBVFVHlq4+Vodv8C/HVxJK1OdPHv1DEl5577jeBTfy33NuqHyKxHer 6Y+90o99yvhyvScFNt9+OoQbW/ZXzWzY4EV/cqLmIUopUaDBQmG4HgaEz PFaOJ354MAldRktHwC3TFJzCtWmdbCfKuaSTAD9HULlIEUD20UF0OHNvk fNGiHvXmCXD5jBikPYkmNQimABJ53/zMn6DlcWIcmL1qqCNPRx053UNZg r3rtltGPF7rS9GV44WHr/QYK0gGodorx0bdnQgBNTJyVdAzPw/QsmvsEp Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10449"; a="273852622" X-IronPort-AV: E=Sophos;i="5.93,261,1654585200"; d="scan'208";a="273852622" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Aug 2022 16:24:55 -0700 X-IronPort-AV: E=Sophos;i="5.93,261,1654585200"; d="scan'208";a="606199634" Received: from iweiny-mobl.amr.corp.intel.com (HELO localhost) ([10.212.42.187]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Aug 2022 16:24:54 -0700 From: ira.weiny@intel.com To: Dan Williams , Bjorn Helgaas , Greg Kroah-Hartman Cc: Ira Weiny , Jonathan Cameron , Alison Schofield , Vishal Verma , Ben Widawsky , linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH V2 2/2] cxl/doe: Request exclusive DOE access Date: Wed, 24 Aug 2022 16:24:50 -0700 Message-Id: <20220824232450.723179-3-ira.weiny@intel.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220824232450.723179-1-ira.weiny@intel.com> References: <20220824232450.723179-1-ira.weiny@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org From: Ira Weiny The PCIE Data Object Exchange (DOE) mailbox is a protocol run over configuration cycles. It assumes one initiator at a time. While the kernel has control of the mailbox user space writes could interfere with the kernel access. Mark DOE mailbox config space exclusive when iterated by the CXL driver. Signed-off-by: Ira Weiny --- drivers/cxl/pci.c | 5 +++++ include/uapi/linux/pci_regs.h | 1 + 2 files changed, 6 insertions(+) diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index faeb5d9d7a7a..5b833eb91543 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -418,6 +418,11 @@ static void devm_cxl_pci_create_doe(struct cxl_dev_state *cxlds) continue; } + if (!pci_request_config_region_exclusive(pdev, off, + PCI_DOE_CAP_SIZE, + dev_name(dev))) + pci_err(pdev, "Failed to exclude DOE registers\n"); + if (xa_insert(&cxlds->doe_mbs, off, doe_mb, GFP_KERNEL)) { dev_err(dev, "xa_insert failed to insert MB @ %x\n", off); diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 57b8e2ffb1dd..f2396bcd09cc 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -1119,6 +1119,7 @@ #define PCI_DOE_STATUS_DATA_OBJECT_READY 0x80000000 /* Data Object Ready */ #define PCI_DOE_WRITE 0x10 /* DOE Write Data Mailbox Register */ #define PCI_DOE_READ 0x14 /* DOE Read Data Mailbox Register */ +#define PCI_DOE_CAP_SIZE (0x14 + 4) /* Size of this register block */ /* DOE Data Object - note not actually registers */ #define PCI_DOE_DATA_OBJECT_HEADER_1_VID 0x0000ffff