| Message ID | 20220831081603.3415-13-rrichter@amd.com |
|---|---|
| State | Superseded |
| Delegated to: | Dan Williams |
| Headers | show |
| Series | cxl: Add support for Restricted CXL hosts (RCD mode) | expand |
On Wed, 31 Aug 2022 10:16:00 +0200 Robert Richter <rrichter@amd.com> wrote: > RCD mode has a different enumeration scheme other than in CXL VH mode. > An RCD is directly connected to an RCH without downstream and upstream > ports showing up in between in the PCI hierarchy. Skip dport > enumeration for RCHs. Upstream and downstream ports of RCH and RCD > will be setup separately in a later patch. > > Introduce the function is_rch_uport() to detect an RCH port. For RCHs > the parent root port is not the "ACPI0017" device and instead does not > have a fw node connected to it. > > Signed-off-by: Robert Richter <rrichter@amd.com> > --- > drivers/cxl/core/pci.c | 20 +++++++++++++++++++- > 1 file changed, 19 insertions(+), 1 deletion(-) > > diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c > index 0dbbe8d39b07..86ed112eb262 100644 > --- a/drivers/cxl/core/pci.c > +++ b/drivers/cxl/core/pci.c > @@ -65,6 +65,15 @@ static int match_add_dports(struct pci_dev *pdev, void *data) > return 0; > } > > +/* > + * A parent of an RCH (CXL 1.1 host) is a plain platform device while > + * a 2.0 host links to the ACPI0017 root device. > + */ > +static inline bool is_rch_uport(struct cxl_port *port) > +{ > + return is_cxl_port(&port->dev) && !port->dev.parent->fwnode; I'm not keen on the presence of fwnode being used to distinguish anything. That's the sort of thing that gets 'fixed' by later patches. Can we check something more specific? > +} > + > /** > * devm_cxl_port_enumerate_dports - enumerate downstream ports of the upstream port > * @port: cxl_port whose ->uport is the upstream of dports to be enumerated > @@ -74,10 +83,19 @@ static int match_add_dports(struct pci_dev *pdev, void *data) > */ > int devm_cxl_port_enumerate_dports(struct cxl_port *port) > { > - struct pci_bus *bus = cxl_port_to_pci_bus(port); > + struct pci_bus *bus; > struct cxl_walk_context ctx; > int type; > > + /* > + * Skip enumeration in Restricted CXL Device mode as the > + * device has been already registered at the host's dport > + * during host discovery. > + */ > + if (is_rch_uport(port)) > + return 0; > + > + bus = cxl_port_to_pci_bus(port); > if (!bus) > return -ENXIO; >
On 31.08.22 12:58:30, Jonathan Cameron wrote: > On Wed, 31 Aug 2022 10:16:00 +0200 > Robert Richter <rrichter@amd.com> wrote: > > +/* > > + * A parent of an RCH (CXL 1.1 host) is a plain platform device while > > + * a 2.0 host links to the ACPI0017 root device. > > + */ > > +static inline bool is_rch_uport(struct cxl_port *port) > > +{ > > + return is_cxl_port(&port->dev) && !port->dev.parent->fwnode; > > I'm not keen on the presence of fwnode being used to distinguish anything. > That's the sort of thing that gets 'fixed' by later patches. > > Can we check something more specific? We actually know the parent device is the root device, so we can check this. Even easier. Thanks, -Robert
diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 0dbbe8d39b07..86ed112eb262 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -65,6 +65,15 @@ static int match_add_dports(struct pci_dev *pdev, void *data) return 0; } +/* + * A parent of an RCH (CXL 1.1 host) is a plain platform device while + * a 2.0 host links to the ACPI0017 root device. + */ +static inline bool is_rch_uport(struct cxl_port *port) +{ + return is_cxl_port(&port->dev) && !port->dev.parent->fwnode; +} + /** * devm_cxl_port_enumerate_dports - enumerate downstream ports of the upstream port * @port: cxl_port whose ->uport is the upstream of dports to be enumerated @@ -74,10 +83,19 @@ static int match_add_dports(struct pci_dev *pdev, void *data) */ int devm_cxl_port_enumerate_dports(struct cxl_port *port) { - struct pci_bus *bus = cxl_port_to_pci_bus(port); + struct pci_bus *bus; struct cxl_walk_context ctx; int type; + /* + * Skip enumeration in Restricted CXL Device mode as the + * device has been already registered at the host's dport + * during host discovery. + */ + if (is_rch_uport(port)) + return 0; + + bus = cxl_port_to_pci_bus(port); if (!bus) return -ENXIO;
RCD mode has a different enumeration scheme other than in CXL VH mode. An RCD is directly connected to an RCH without downstream and upstream ports showing up in between in the PCI hierarchy. Skip dport enumeration for RCHs. Upstream and downstream ports of RCH and RCD will be setup separately in a later patch. Introduce the function is_rch_uport() to detect an RCH port. For RCHs the parent root port is not the "ACPI0017" device and instead does not have a fw node connected to it. Signed-off-by: Robert Richter <rrichter@amd.com> --- drivers/cxl/core/pci.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-)