| Message ID | 20221006233702.18532-1-gregory.price@memverge.com |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/2] hw/cxl: set cxl-type3 device type to PCI_CLASS_MEMORY_CXL | expand |
On Thu, 6 Oct 2022 19:37:01 -0400 Gregory Price <gourry.memverge@gmail.com> wrote: > Current code sets to STORAGE_EXPRESS and then overrides it. > > Signed-off-by: Gregory Price <gregory.price@memverge.com> I'm carry the same patch after you reported it the other day. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > --- > hw/mem/cxl_type3.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c > index ada2108fac..1837c1c83a 100644 > --- a/hw/mem/cxl_type3.c > +++ b/hw/mem/cxl_type3.c > @@ -146,7 +146,6 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp) > } > > pci_config_set_prog_interface(pci_conf, 0x10); > - pci_config_set_class(pci_conf, PCI_CLASS_MEMORY_CXL); > > pcie_endpoint_cap_init(pci_dev, 0x80); > cxl_cstate->dvsec_offset = 0x100; > @@ -335,7 +334,7 @@ static void ct3_class_init(ObjectClass *oc, void *data) > > pc->realize = ct3_realize; > pc->exit = ct3_exit; > - pc->class_id = PCI_CLASS_STORAGE_EXPRESS; > + pc->class_id = PCI_CLASS_MEMORY_CXL; > pc->vendor_id = PCI_VENDOR_ID_INTEL; > pc->device_id = 0xd93; /* LVF for now */ > pc->revision = 1;
On Thu, 06 Oct 2022, Gregory Price wrote: >Current code sets to STORAGE_EXPRESS and then overrides it. Good catch. Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>
On Thu, 06 Oct 2022, Gregory Price wrote: >Current code sets to STORAGE_EXPRESS and then overrides it. Good catch. Reviewed-by: Davidlohr Bueso <dave@stgolabs.net> > >Signed-off-by: Gregory Price <gregory.price@memverge.com> >--- > hw/mem/cxl_type3.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > >diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c >index ada2108fac..1837c1c83a 100644 >--- a/hw/mem/cxl_type3.c >+++ b/hw/mem/cxl_type3.c >@@ -146,7 +146,6 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp) > } > > pci_config_set_prog_interface(pci_conf, 0x10); >- pci_config_set_class(pci_conf, PCI_CLASS_MEMORY_CXL); > > pcie_endpoint_cap_init(pci_dev, 0x80); > cxl_cstate->dvsec_offset = 0x100; >@@ -335,7 +334,7 @@ static void ct3_class_init(ObjectClass *oc, void *data) > > pc->realize = ct3_realize; > pc->exit = ct3_exit; >- pc->class_id = PCI_CLASS_STORAGE_EXPRESS; >+ pc->class_id = PCI_CLASS_MEMORY_CXL; > pc->vendor_id = PCI_VENDOR_ID_INTEL; > pc->device_id = 0xd93; /* LVF for now */ > pc->revision = 1; >-- >2.37.3 >
On Thu, Oct 06, 2022 at 07:37:01PM -0400, Gregory Price wrote: > Current code sets to STORAGE_EXPRESS and then overrides it. > > Signed-off-by: Gregory Price <gregory.price@memverge.com> If you expect me to merge it you need to CC me. Also, do we need this separately from the series? > --- > hw/mem/cxl_type3.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c > index ada2108fac..1837c1c83a 100644 > --- a/hw/mem/cxl_type3.c > +++ b/hw/mem/cxl_type3.c > @@ -146,7 +146,6 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp) > } > > pci_config_set_prog_interface(pci_conf, 0x10); > - pci_config_set_class(pci_conf, PCI_CLASS_MEMORY_CXL); > > pcie_endpoint_cap_init(pci_dev, 0x80); > cxl_cstate->dvsec_offset = 0x100; > @@ -335,7 +334,7 @@ static void ct3_class_init(ObjectClass *oc, void *data) > > pc->realize = ct3_realize; > pc->exit = ct3_exit; > - pc->class_id = PCI_CLASS_STORAGE_EXPRESS; > + pc->class_id = PCI_CLASS_MEMORY_CXL; > pc->vendor_id = PCI_VENDOR_ID_INTEL; > pc->device_id = 0xd93; /* LVF for now */ > pc->revision = 1; > -- > 2.37.3 > >
I believe this was dropped from my line because Jonathan carried a similar commit on his branch. Happy to push it up again as a separate commit if that is what you want. Noted for the future on upstreams -----Original Message----- From: Michael S. Tsirkin <mst@redhat.com> Sent: Wednesday, October 26, 2022 4:06 PM To: Gregory Price <gourry.memverge@gmail.com> Cc: qemu-devel@nongnu.org; jonathan.cameron@huawei.com; linux-cxl@vger.kernel.org; alison.schofield@intel.com; dave@stgolabs.net; a.manzanares@samsung.com; bwidawsk@kernel.org; Gregory Price <gregory.price@memverge.com> Subject: Re: [PATCH 1/2] hw/cxl: set cxl-type3 device type to PCI_CLASS_MEMORY_CXL On Thu, Oct 06, 2022 at 07:37:01PM -0400, Gregory Price wrote: > Current code sets to STORAGE_EXPRESS and then overrides it. > > Signed-off-by: Gregory Price <gregory.price@memverge.com> If you expect me to merge it you need to CC me. Also, do we need this separately from the series? > --- > hw/mem/cxl_type3.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index > ada2108fac..1837c1c83a 100644 > --- a/hw/mem/cxl_type3.c > +++ b/hw/mem/cxl_type3.c > @@ -146,7 +146,6 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp) > } > > pci_config_set_prog_interface(pci_conf, 0x10); > - pci_config_set_class(pci_conf, PCI_CLASS_MEMORY_CXL); > > pcie_endpoint_cap_init(pci_dev, 0x80); > cxl_cstate->dvsec_offset = 0x100; @@ -335,7 +334,7 @@ static void > ct3_class_init(ObjectClass *oc, void *data) > > pc->realize = ct3_realize; > pc->exit = ct3_exit; > - pc->class_id = PCI_CLASS_STORAGE_EXPRESS; > + pc->class_id = PCI_CLASS_MEMORY_CXL; > pc->vendor_id = PCI_VENDOR_ID_INTEL; > pc->device_id = 0xd93; /* LVF for now */ > pc->revision = 1; > -- > 2.37.3 > >
He does but in the end he sends patches not pull requests. I don't care really as long as someone will send it up. On Wed, Oct 26, 2022 at 08:09:45PM +0000, Gregory Price wrote: > I believe this was dropped from my line because Jonathan carried a similar commit on his branch. > > Happy to push it up again as a separate commit if that is what you want. > > Noted for the future on upstreams > > -----Original Message----- > From: Michael S. Tsirkin <mst@redhat.com> > Sent: Wednesday, October 26, 2022 4:06 PM > To: Gregory Price <gourry.memverge@gmail.com> > Cc: qemu-devel@nongnu.org; jonathan.cameron@huawei.com; linux-cxl@vger.kernel.org; alison.schofield@intel.com; dave@stgolabs.net; a.manzanares@samsung.com; bwidawsk@kernel.org; Gregory Price <gregory.price@memverge.com> > Subject: Re: [PATCH 1/2] hw/cxl: set cxl-type3 device type to PCI_CLASS_MEMORY_CXL > > On Thu, Oct 06, 2022 at 07:37:01PM -0400, Gregory Price wrote: > > Current code sets to STORAGE_EXPRESS and then overrides it. > > > > Signed-off-by: Gregory Price <gregory.price@memverge.com> > > If you expect me to merge it you need to CC me. > Also, do we need this separately from the series? > > > --- > > hw/mem/cxl_type3.c | 3 +-- > > 1 file changed, 1 insertion(+), 2 deletions(-) > > > > diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index > > ada2108fac..1837c1c83a 100644 > > --- a/hw/mem/cxl_type3.c > > +++ b/hw/mem/cxl_type3.c > > @@ -146,7 +146,6 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp) > > } > > > > pci_config_set_prog_interface(pci_conf, 0x10); > > - pci_config_set_class(pci_conf, PCI_CLASS_MEMORY_CXL); > > > > pcie_endpoint_cap_init(pci_dev, 0x80); > > cxl_cstate->dvsec_offset = 0x100; @@ -335,7 +334,7 @@ static void > > ct3_class_init(ObjectClass *oc, void *data) > > > > pc->realize = ct3_realize; > > pc->exit = ct3_exit; > > - pc->class_id = PCI_CLASS_STORAGE_EXPRESS; > > + pc->class_id = PCI_CLASS_MEMORY_CXL; > > pc->vendor_id = PCI_VENDOR_ID_INTEL; > > pc->device_id = 0xd93; /* LVF for now */ > > pc->revision = 1; > > -- > > 2.37.3 > > > >
On Wed, Oct 26, 2022 at 04:11:29PM -0400, Michael S. Tsirkin wrote: > He does but in the end he sends patches not pull requests. > I don't care really as long as someone will send it up. > Jonathan will submit this, it's not a critical issue so it can wait for the larger feature set.
On Wed, 26 Oct 2022 17:07:53 -0400 Gregory Price <gregory.price@memverge.com> wrote: > On Wed, Oct 26, 2022 at 04:11:29PM -0400, Michael S. Tsirkin wrote: > > He does but in the end he sends patches not pull requests. > > I don't care really as long as someone will send it up. > > > > Jonathan will submit this, it's not a critical issue so it can wait for > the larger feature set. Sure, I'll roll it with a few other similarly minor fixes in a few days as a patch set. Jonathan
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index ada2108fac..1837c1c83a 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -146,7 +146,6 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp) } pci_config_set_prog_interface(pci_conf, 0x10); - pci_config_set_class(pci_conf, PCI_CLASS_MEMORY_CXL); pcie_endpoint_cap_init(pci_dev, 0x80); cxl_cstate->dvsec_offset = 0x100; @@ -335,7 +334,7 @@ static void ct3_class_init(ObjectClass *oc, void *data) pc->realize = ct3_realize; pc->exit = ct3_exit; - pc->class_id = PCI_CLASS_STORAGE_EXPRESS; + pc->class_id = PCI_CLASS_MEMORY_CXL; pc->vendor_id = PCI_VENDOR_ID_INTEL; pc->device_id = 0xd93; /* LVF for now */ pc->revision = 1;
Current code sets to STORAGE_EXPRESS and then overrides it. Signed-off-by: Gregory Price <gregory.price@memverge.com> --- hw/mem/cxl_type3.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)