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Wysocki" , Len Brown , Jonathan Cameron , "Davidlohr Bueso" , Robert Richter Subject: [PATCH v2 11/12] cxl: Factor out code in match_add_dports() to pci_dev_add_dport() Date: Tue, 18 Oct 2022 15:23:39 +0200 Message-ID: <20221018132341.76259-12-rrichter@amd.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221018132341.76259-1-rrichter@amd.com> References: <20221018132341.76259-1-rrichter@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT028:EE_|CH0PR12MB5266:EE_ X-MS-Office365-Filtering-Correlation-Id: 5f9f280b-fa20-4503-465a-08dab10c28db X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: nGWAmxUBc5wQVTyVa10/bDMqRGlfRFQRZNB+5Y1WJa5CTt+8urbdwRDM+Ml3Rl4B2NV/rOMYJFzquRoCTvF7zyNy/eVV8GqYD8IVRUP/pwhkhrjJuQq+RwlvLZVSYv1RiCWA6qERINYMueD9s7Wt3rp2LESC2Pbqscbth4V7uAQbrYPOR1JtCSA989JXp/VMKol5UysUl/FoXM6W/a44fboMjFA32vZsVrx/PJ186djf+hdUxULSoz14QmdWeqzPkJ2ximfYN7Fb9I6l4jCd9xgFSY0a9WHN2ulGHibJgME/A20D6AGml/cDHKUmziEXgXlTDV8CuOR3XAeVfqsA6PXVQpV2w3J8cNwh/1Ykx7xzQNBdxYfEnGTlSTy9Fpoaba1OnAkG0WR9WjJ4BkPoO/v+V8RvOJ94l8REr28bjBH4OtI6IA2cJpBlTmCgZKWrn7Xo9zK76qQLr7nPzjpgxx22uWKgnybZhkHQhdJAbsqPjrXSBod6oXq0a5/uCxTSpLFEmhD65TVL08m9R27Cgpwj0reoPCS1Mhx4avOucBG6YV2V3y0ifBD6Bwf5j7YoAL6PtcgjcHcZkEorJqyB/wN0nlwCdd+aAEFT6Luyg/TSQIvMJohuGbquHd40uX+42jeE8pUB16wmfhxUtuc7C7hR1Uhvlzz2t+5eqXbVlrleR9wa/RRWQWm0esmOoA+fc2b31wd04Gz7LS+WcPWWejEeVMqPslg8uC5bpElPL3jqGYKMSi6KVZnlYzOQXpjIzOqZCx11l7Xr0rjd2Zg5jZy7phDKqOhx2qg/EWgjR5o= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(346002)(396003)(136003)(376002)(39860400002)(451199015)(40470700004)(36840700001)(46966006)(110136005)(54906003)(4326008)(8676002)(7416002)(5660300002)(316002)(40460700003)(70586007)(70206006)(36860700001)(6666004)(478600001)(82310400005)(2906002)(41300700001)(36756003)(8936002)(83380400001)(186003)(1076003)(336012)(16526019)(426003)(47076005)(82740400003)(40480700001)(356005)(26005)(2616005)(81166007)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Oct 2022 13:25:00.9216 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5f9f280b-fa20-4503-465a-08dab10c28db X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT028.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5266 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org Factor out the code to register a PCI device's dport to a port. It will be reused to implement RCD mode. Signed-off-by: Robert Richter --- drivers/cxl/core/pci.c | 37 ++++++++++++++++++++++++++----------- 1 file changed, 26 insertions(+), 11 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 8271b8abde7a..667de4f125f6 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -29,14 +29,32 @@ struct cxl_walk_context { int count; }; +static int pci_dev_add_dport(struct pci_dev *pdev, struct cxl_port *port, + resource_size_t component_reg_phys) +{ + struct cxl_dport *dport; + u32 lnkcap, port_num; + + if (pci_read_config_dword(pdev, pci_pcie_cap(pdev) + PCI_EXP_LNKCAP, + &lnkcap)) + return -ENXIO; + + port_num = FIELD_GET(PCI_EXP_LNKCAP_PN, lnkcap); + dport = devm_cxl_add_dport(port, &pdev->dev, port_num, + component_reg_phys); + if (IS_ERR(dport)) + return PTR_ERR(dport); + + return 0; +} + static int match_add_dports(struct pci_dev *pdev, void *data) { struct cxl_walk_context *ctx = data; struct cxl_port *port = ctx->port; int type = pci_pcie_type(pdev); struct cxl_register_map map; - struct cxl_dport *dport; - u32 lnkcap, port_num; + resource_size_t component_reg_phys; int rc; if (pdev->bus != ctx->bus) @@ -45,21 +63,18 @@ static int match_add_dports(struct pci_dev *pdev, void *data) return 0; if (type != ctx->type) return 0; - if (pci_read_config_dword(pdev, pci_pcie_cap(pdev) + PCI_EXP_LNKCAP, - &lnkcap)) - return -ENXIO; rc = cxl_find_regblock(pdev, CXL_REGLOC_RBI_COMPONENT, &map); if (rc) dev_dbg(&port->dev, "failed to find component registers\n"); - port_num = FIELD_GET(PCI_EXP_LNKCAP_PN, lnkcap); - dport = devm_cxl_add_dport(port, &pdev->dev, port_num, - cxl_regmap_to_base(pdev, &map)); - if (IS_ERR(dport)) { - ctx->error = PTR_ERR(dport); - return PTR_ERR(dport); + component_reg_phys = cxl_regmap_to_base(pdev, &map); + rc = pci_dev_add_dport(pdev, port, component_reg_phys); + if (rc) { + ctx->error = rc; + return rc; } + ctx->count++; return 0;