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Wysocki" , Len Brown , Jonathan Cameron , "Davidlohr Bueso" , Dave Jiang , Robert Richter Subject: [PATCH v3 7/9] cxl/pci: Factor out code in match_add_dports() to pci_dev_add_dport() Date: Wed, 9 Nov 2022 11:40:57 +0100 Message-ID: <20221109104059.766720-8-rrichter@amd.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221109104059.766720-1-rrichter@amd.com> References: <20221109104059.766720-1-rrichter@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT031:EE_|DM4PR12MB5216:EE_ X-MS-Office365-Filtering-Correlation-Id: e76397c1-a1ee-485a-0157-08dac23efe48 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 7zqoFqo/jzW42iUUSv6lS1sllGBlfaJDATCNc9zvjjUZfcTG408m4+JKnlVpOlkmBc6qMfPL6wMO+qx07ZssHQCJT4uVQ4bb4d3ekqJNnvgIakJcCXo5gxdksSa3MrImo2V/Q6O50QZffQbGaG1YPwIWSHdmkVnUtfpJrINmS2AvkmUEf8UpXx9XfZljLvReuycWcf4fXZ7ncLWc2vhMeIOt/f+D+csduUiz/dsoVTSwRiqVbC3oGmkI/fYWVybySJaCx8cbZLI/tPIxHf4SNMCFoCnzqhOCo+rRhbbCmW/TXqTAA1bxYDKGfYBvNw2y/+6Ik4tZqyK2b1tph6o3Drw0U4uPtczaflI4NK/RP5cTUosiz1T3Tl1UOyFyKPOTWONHHc0jZOlsXiCWllDsVxqKwwVETvB6TLbmBeAp0/iM45ZaDAGLPp5bQ92DAHqaxU2/+foqjT5T+NPlDdEJ2eQCi7lwn6CtB4H1GKMgulcNN+Gyd+AE4PPIeaE3z37viwGcrvOq5ak1gncZMMY4BfAwHSeKyPmK0tSVk2tofjVRe2hASReDLhf90ceJ6aQ9CTkb8YN8sKb47jOi+YRdBTdhHMAz297FMKPAoOYgMegYDpOnfiUlx3EHkmArY4VAgLP4iLhy3leCqc0cT1+9GbQM3WBCHSRSsAHyEB2bsm2ENivP6zYTjMy7fLFM/taejoDpBrI1NX8+URmgxMk9CPqfTNZCKalzE+bX3OH5l9wj4PfCpiooAPG7WyzZql5yx5uAjXdvkcq4PAmWqB9aj8WKUCjzz9fS/d0DonR0RP0= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(376002)(39860400002)(346002)(396003)(136003)(451199015)(36840700001)(46966006)(40470700004)(26005)(82740400003)(356005)(36860700001)(81166007)(82310400005)(8936002)(70586007)(41300700001)(8676002)(70206006)(4326008)(7416002)(5660300002)(110136005)(316002)(478600001)(40480700001)(54906003)(6666004)(40460700003)(426003)(47076005)(83380400001)(336012)(16526019)(1076003)(2906002)(186003)(36756003)(2616005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Nov 2022 10:41:43.5770 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e76397c1-a1ee-485a-0157-08dac23efe48 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT031.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5216 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org Factor out the code to register a PCI device's dport to a port. It will be reused to implement RCD mode. Signed-off-by: Robert Richter --- drivers/cxl/core/pci.c | 37 ++++++++++++++++++++++++++----------- 1 file changed, 26 insertions(+), 11 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 8271b8abde7a..667de4f125f6 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -29,14 +29,32 @@ struct cxl_walk_context { int count; }; +static int pci_dev_add_dport(struct pci_dev *pdev, struct cxl_port *port, + resource_size_t component_reg_phys) +{ + struct cxl_dport *dport; + u32 lnkcap, port_num; + + if (pci_read_config_dword(pdev, pci_pcie_cap(pdev) + PCI_EXP_LNKCAP, + &lnkcap)) + return -ENXIO; + + port_num = FIELD_GET(PCI_EXP_LNKCAP_PN, lnkcap); + dport = devm_cxl_add_dport(port, &pdev->dev, port_num, + component_reg_phys); + if (IS_ERR(dport)) + return PTR_ERR(dport); + + return 0; +} + static int match_add_dports(struct pci_dev *pdev, void *data) { struct cxl_walk_context *ctx = data; struct cxl_port *port = ctx->port; int type = pci_pcie_type(pdev); struct cxl_register_map map; - struct cxl_dport *dport; - u32 lnkcap, port_num; + resource_size_t component_reg_phys; int rc; if (pdev->bus != ctx->bus) @@ -45,21 +63,18 @@ static int match_add_dports(struct pci_dev *pdev, void *data) return 0; if (type != ctx->type) return 0; - if (pci_read_config_dword(pdev, pci_pcie_cap(pdev) + PCI_EXP_LNKCAP, - &lnkcap)) - return -ENXIO; rc = cxl_find_regblock(pdev, CXL_REGLOC_RBI_COMPONENT, &map); if (rc) dev_dbg(&port->dev, "failed to find component registers\n"); - port_num = FIELD_GET(PCI_EXP_LNKCAP_PN, lnkcap); - dport = devm_cxl_add_dport(port, &pdev->dev, port_num, - cxl_regmap_to_base(pdev, &map)); - if (IS_ERR(dport)) { - ctx->error = PTR_ERR(dport); - return PTR_ERR(dport); + component_reg_phys = cxl_regmap_to_base(pdev, &map); + rc = pci_dev_add_dport(pdev, port, component_reg_phys); + if (rc) { + ctx->error = rc; + return rc; } + ctx->count++; return 0;