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Tue, 20 Dec 2022 18:26:41 +0000 (GMT) X-AuditID: cbfec36f-a9bfe7000002c95c-0a-63a1fe6153e9 Received: from SSI-EX2.ssi.samsung.com ( [105.128.2.145]) by ussmgxs3new.samsung.com (USCPEXMTA) with SMTP id F2.48.07107.16EF1A36; Tue, 20 Dec 2022 13:26:41 -0500 (EST) Received: from SSI-EX2.ssi.samsung.com (105.128.2.227) by SSI-EX2.ssi.samsung.com (105.128.2.227) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.1.2375.24; Tue, 20 Dec 2022 10:26:40 -0800 Received: from SSI-EX2.ssi.samsung.com ([105.128.2.227]) by SSI-EX2.ssi.samsung.com ([105.128.2.227]) with mapi id 15.01.2375.024; Tue, 20 Dec 2022 10:26:40 -0800 From: Fan Ni To: "linux-cxl@vger.kernel.org" CC: "dan.j.williams@intel.com" , "vishal.l.verma@intel.com" , "dave@stgolabs.net" , Adam Manzanares , "sunfishho12@gmail.com" , Fan Ni Subject: [ndctl PATCH 1/2] cxl-list: add `parent_dport` to cxl_port/memdev objects Thread-Topic: [ndctl PATCH 1/2] cxl-list: add `parent_dport` to cxl_port/memdev objects Thread-Index: AQHZFKCaOmcvc8eDq0mTxCsoX7geTw== Date: Tue, 20 Dec 2022 18:26:40 +0000 Message-ID: <20221220182510.2734032-2-fan.ni@samsung.com> In-Reply-To: <20221220182510.2734032-1-fan.ni@samsung.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [105.128.2.176] MIME-Version: 1.0 X-CFilter-Loop: Reflected X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprIKsWRmVeSWpSXmKPExsWy7djX87qJ/xYmG7TNU7aYPvUCo8Xqm2sY Lc7POsVi0fhzEaPFrQnHmBxYPXbOusvusXjPSyaPqbPrPT5vkgtgieKySUnNySxLLdK3S+DK WHqji63gqWbF5V/32BsYe5S7GDk5JARMJL4t7GbvYuTiEBJYySjx6u9dKKeVSeLQ78dsXYwc YFWnnmdBxNcyStxb/Amq6BOjxLRnU5ggnGWMEo93fWYCmcsmoCixr2s7G4gtImAtMaFhCRtI EbPATCaJq9+mgxUJC4RItL74ww5RFClx+vdxVghbT2Lan/fMIDaLgKrEzevbwWxeAUuJV3un gfVyClhJfN6ymhHEZhQQk/h+ag1YnFlAXOLWk/lMEM8JSiyavYcZwhaT+LfrIRuErShx//tL doh6PYkbU6ewQdjaEssWvobaJShxcuYTFoh6SYmDK26wgDwgIbCWQ+LRvytQg1wkevt/Qi2Q lpi+5jJUQ75Ez44TjBB2hcTL2SvYIWxriYV/1kMdyifx99cjxgmMyrOQ3D0LyU2zkNw0C8lN CxhZVjGKlxYX56anFhvlpZbrFSfmFpfmpesl5+duYgSmmtP/DufvYLx+66PeIUYmDsZDjBIc zEoivBeOLEwW4k1JrKxKLcqPLyrNSS0+xCjNwaIkztu9dX6ykEB6YklqdmpqQWoRTJaJg1Oq galF5/XJiP35PkJ2q6eelCqfUWiqa3PuZn4gx6vreiVX/nR4fH0sLiWz4bPudYn9px/c10p+ wLL59ZoVaw06mfvem94R6slsOHzg89frfAm72uYedj9uL69s/ijamiFrhfCcnYJyj+4fmlMu sHTLhqSJVnGMK/j2/WIUeimz/bDcWattArX35S/ENd16d1jm2OR3J5mcFjbIX7LfnOqzVWFq 6tcSYe7NX00+t56InKivY55fUzapweLrLNGe8jabH+vliqwW325ceafddoa86uMNKwzL5x6J mRa37MzrVfkRX3P7jLQ2LXH5KBP+xZdtUd21d+l3Ocs2urRGlGi8XH3vSFPjlPP+f84Ji69P Uj2mxFKckWioxVxUnAgAO43/WKQDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrAIsWRmVeSWpSXmKPExsWS2cA0UTfx38Jkg2XNIhbTp15gtFh9cw2j xflZp1gsGn8uYrS4NeEYkwOrx85Zd9k9Fu95yeQxdXa9x+dNcgEsUVw2Kak5mWWpRfp2CVwZ S290sRU81ay4/OseewNjj3IXIweHhICJxKnnWV2MnBxCAqsZJVZe1YKwPzFKLDwo1cXIBWQv Y5R42PKVFSTBJqAosa9rOxuILSJgLTGhYQkbSBGzwEwmiavfpjOBJIQFQiRaX/xhhyiKlOjv vwtl60lM+/OeGcRmEVCVuHl9O5jNK2Ap8WrvNCaIzZYSbesfgi3jFLCS+LxlNSOIzSggJvH9 1BqwGmYBcYlbT+aD2RICAhJL9pxnhrBFJV4+/scKYStK3P/+kh2iXk/ixtQpbBC2tsSyha+h 9gpKnJz5hAWiXlLi4IobLBMYxWchWTELSfssJO2zkLQvYGRZxSheWlycm15RbJyXWq5XnJhb XJqXrpecn7uJERiJp/8djtnBeO/WR71DjEwcjIcYJTiYlUR4LxxZmCzEm5JYWZValB9fVJqT WnyIUZqDRUmc1yN2YryQQHpiSWp2ampBahFMlomDU6qBycC6a6LOOcO65C7/gOkTJl455iYe lrykO0fj7961H9f8lZ1Rt2A5f7wW7/v7vbc1/m6etH+vssefuW3lvfXfK66z3HovG9sjKyiy MOueXEC/3OMLWQ4LjexXCvKoLOyV/yhT6nHwuuC0pku+9uKsijt/Tn03N7BwSZVJ6JfqmqaN SWrH/3b0yRTX+3YwZdz9a+nz3v33mZW939yt1/fFhRf87ppzgcO3oiP60YYgtddnnJ8wMmv/ X/v9SCfDLcFD666YCBsH6JVnVfQVP9EtnfbP+VCY3c2zvb8DJ5548ve9tnCc4EmW14ILMl5c 8/tlz8DTu3L2vbPa6iwZkXOCPK46FAdFhajr1ORvmaegxFKckWioxVxUnAgAXfF2bjMDAAA= X-CMS-MailID: 20221220182641uscas1p24e70ddc9f912de0f3912028420854fb1 CMS-TYPE: 301P X-CMS-RootMailID: 20221220182641uscas1p24e70ddc9f912de0f3912028420854fb1 References: <20221220182510.2734032-1-fan.ni@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org The parent_dport attribute reprents the downstream port that the current device (cxl_port/cxl_memdev) is attached to. It will help to track the topology when plotting the cxl graph Signed-off-by: Fan Ni --- cxl/json.c | 8 ++++++++ cxl/lib/libcxl.c | 39 +++++++++++++++++++++++++++++++++++++++ cxl/lib/libcxl.sym | 6 ++++++ cxl/lib/private.h | 1 + cxl/libcxl.h | 2 ++ 5 files changed, 56 insertions(+) diff --git a/cxl/json.c b/cxl/json.c index 63c1751..ac1b0b5 100644 --- a/cxl/json.c +++ b/cxl/json.c @@ -348,6 +348,10 @@ struct json_object *util_cxl_memdev_to_json(struct cxl_memdev *memdev, if (jobj) json_object_object_add(jdev, "host", jobj); + jobj = json_object_new_string(cxl_memdev_get_parent_dport(memdev)); + if (jobj) + json_object_object_add(jdev, "parent_dport", jobj); + if (!cxl_memdev_is_enabled(memdev)) { jobj = json_object_new_string("disabled"); if (jobj) @@ -769,6 +773,10 @@ static struct json_object *__util_cxl_port_to_json(struct cxl_port *port, if (jobj) json_object_object_add(jport, "host", jobj); + jobj = json_object_new_string(cxl_port_get_parent_dport(port)); + if (jobj) + json_object_object_add(jport, "parent_dport", jobj); + jobj = json_object_new_int(cxl_port_get_depth(port)); if (jobj) json_object_object_add(jport, "depth", jobj); diff --git a/cxl/lib/libcxl.c b/cxl/lib/libcxl.c index e8c5d44..27ffee0 100644 --- a/cxl/lib/libcxl.c +++ b/cxl/lib/libcxl.c @@ -1267,6 +1267,16 @@ CXL_EXPORT const char *cxl_memdev_get_firmware_verison(struct cxl_memdev *memdev return memdev->firmware_version; } +CXL_EXPORT const char *cxl_memdev_get_parent_dport(struct cxl_memdev *memdev) +{ + struct cxl_port *port = cxl_endpoint_get_port(memdev->endpoint); + + if (port) + return cxl_port_get_parent_dport(port); + + return NULL; +} + static void bus_invalidate(struct cxl_bus *bus) { struct cxl_ctx *ctx = cxl_bus_get_ctx(bus); @@ -1447,6 +1457,24 @@ CXL_EXPORT int cxl_memdev_nvdimm_bridge_active(struct cxl_memdev *memdev) return is_enabled(path); } +static struct cxl_dport *cxl_port_find_parent_dport(struct cxl_port *port, + struct cxl_port *parent_port) +{ + struct cxl_dport *dport; + + if (parent_port && parent_port->nr_dports) { + cxl_dport_foreach(parent_port, dport) { + /* HB ACPI0016 can have only one dport and being itself */ + if (!strcmp(port->uport, dport->dev_path)) + return NULL; + if (strstr(port->uport, dport->dev_path)) + return dport; + } + } + + return NULL; +} + static int cxl_port_init(struct cxl_port *port, struct cxl_port *parent_port, enum cxl_port_type type, struct cxl_ctx *ctx, int id, const char *cxlport_base) @@ -1486,6 +1514,8 @@ static int cxl_port_init(struct cxl_port *port, struct cxl_port *parent_port, if (!port->uport) goto err; + port->parent_dport = cxl_port_find_parent_dport(port, parent_port); + sprintf(path, "%s/modalias", cxlport_base); if (sysfs_read_attr(ctx, path, buf) == 0) port->module = util_modalias_to_module(ctx, buf); @@ -2404,6 +2434,15 @@ CXL_EXPORT struct cxl_port *cxl_port_get_parent(struct cxl_port *port) return port->parent; } +CXL_EXPORT const char *cxl_port_get_parent_dport(struct cxl_port *port) +{ + if (port->parent_dport) + return devpath_to_devname(port->parent_dport->dev_path); + else if (port->parent) + return devpath_to_devname(port->parent->uport); + return NULL; +} + CXL_EXPORT bool cxl_port_is_root(struct cxl_port *port) { return port->type == CXL_PORT_ROOT; diff --git a/cxl/lib/libcxl.sym b/cxl/lib/libcxl.sym index 8bb91e0..33f3bba 100644 --- a/cxl/lib/libcxl.sym +++ b/cxl/lib/libcxl.sym @@ -217,3 +217,9 @@ global: cxl_decoder_get_max_available_extent; cxl_decoder_get_region; } LIBCXL_2; + +LIBCXL_4 { +global: + cxl_memdev_get_parent_dport; + cxl_port_get_parent_dport; +}LIBCXL_3; diff --git a/cxl/lib/private.h b/cxl/lib/private.h index 437eade..ee7d769 100644 --- a/cxl/lib/private.h +++ b/cxl/lib/private.h @@ -71,6 +71,7 @@ struct cxl_port { struct cxl_bus *bus; enum cxl_port_type type; struct cxl_port *parent; + struct cxl_dport *parent_dport; struct kmod_module *module; struct list_node list; struct list_head child_ports; diff --git a/cxl/libcxl.h b/cxl/libcxl.h index 9fe4e99..588ad00 100644 --- a/cxl/libcxl.h +++ b/cxl/libcxl.h @@ -34,6 +34,7 @@ void cxl_set_private_data(struct cxl_ctx *ctx, void *data); void *cxl_get_private_data(struct cxl_ctx *ctx); struct cxl_memdev; +const char *cxl_memdev_get_parent_dport(struct cxl_memdev *memdev); struct cxl_memdev *cxl_memdev_get_first(struct cxl_ctx *ctx); struct cxl_memdev *cxl_memdev_get_next(struct cxl_memdev *memdev); int cxl_memdev_get_id(struct cxl_memdev *memdev); @@ -81,6 +82,7 @@ int cxl_bus_disable_invalidate(struct cxl_bus *bus); bus = cxl_bus_get_next(bus)) struct cxl_port; +const char *cxl_port_get_parent_dport(struct cxl_port *port); struct cxl_port *cxl_port_get_first(struct cxl_port *parent); struct cxl_port *cxl_port_get_next(struct cxl_port *port); const char *cxl_port_get_devname(struct cxl_port *port);