diff mbox series

[v4,5/8] hw/mem/cxl-type3: Add AER extended capability

Message ID 20230217172924.25239-6-Jonathan.Cameron@huawei.com
State Superseded
Headers show
Series hw/cxl: RAS error emulation and injection | expand

Commit Message

Jonathan Cameron Feb. 17, 2023, 5:29 p.m. UTC 
This enables AER error injection to function as expected.
It is intended as a building block in enabling CXL RAS error injection
in the following patches.

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 hw/mem/cxl_type3.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

Comments

Dave Jiang Feb. 17, 2023, 9:47 p.m. UTC | #1 
On 2/17/23 10:29 AM, Jonathan Cameron wrote:
> This enables AER error injection to function as expected.
> It is intended as a building block in enabling CXL RAS error injection
> in the following patches.
> 
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

Reviewed-by: Dave Jiang <dave.jiang@intel.com>

> ---
>   hw/mem/cxl_type3.c | 13 +++++++++++++
>   1 file changed, 13 insertions(+)
> 
> diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
> index 217a5e639b..6cdd988d1d 100644
> --- a/hw/mem/cxl_type3.c
> +++ b/hw/mem/cxl_type3.c
> @@ -250,6 +250,7 @@ static void ct3d_config_write(PCIDevice *pci_dev, uint32_t addr, uint32_t val,
>   
>       pcie_doe_write_config(&ct3d->doe_cdat, addr, val, size);
>       pci_default_write_config(pci_dev, addr, val, size);
> +    pcie_aer_write_config(pci_dev, addr, val, size);
>   }
>   
>   /*
> @@ -452,8 +453,19 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp)
>       cxl_cstate->cdat.free_cdat_table = ct3_free_cdat_table;
>       cxl_cstate->cdat.private = ct3d;
>       cxl_doe_cdat_init(cxl_cstate, errp);
> +
> +    pcie_cap_deverr_init(pci_dev);
> +    /* Leave a bit of room for expansion */
> +    rc = pcie_aer_init(pci_dev, PCI_ERR_VER, 0x200, PCI_ERR_SIZEOF, NULL);
> +    if (rc) {
> +        goto err_release_cdat;
> +    }
> +
>       return;
>   
> +err_release_cdat:
> +    cxl_doe_cdat_release(cxl_cstate);
> +    g_free(regs->special_ops);
>   err_address_space_free:
>       address_space_destroy(&ct3d->hostmem_as);
>       return;
> @@ -465,6 +477,7 @@ static void ct3_exit(PCIDevice *pci_dev)
>       CXLComponentState *cxl_cstate = &ct3d->cxl_cstate;
>       ComponentRegisters *regs = &cxl_cstate->crb;
>   
> +    pcie_aer_exit(pci_dev);
>       cxl_doe_cdat_release(cxl_cstate);
>       g_free(regs->special_ops);
>       address_space_destroy(&ct3d->hostmem_as);
diff mbox series

Patch

diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index 217a5e639b..6cdd988d1d 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw/mem/cxl_type3.c
@@ -250,6 +250,7 @@  static void ct3d_config_write(PCIDevice *pci_dev, uint32_t addr, uint32_t val,
 
     pcie_doe_write_config(&ct3d->doe_cdat, addr, val, size);
     pci_default_write_config(pci_dev, addr, val, size);
+    pcie_aer_write_config(pci_dev, addr, val, size);
 }
 
 /*
@@ -452,8 +453,19 @@  static void ct3_realize(PCIDevice *pci_dev, Error **errp)
     cxl_cstate->cdat.free_cdat_table = ct3_free_cdat_table;
     cxl_cstate->cdat.private = ct3d;
     cxl_doe_cdat_init(cxl_cstate, errp);
+
+    pcie_cap_deverr_init(pci_dev);
+    /* Leave a bit of room for expansion */
+    rc = pcie_aer_init(pci_dev, PCI_ERR_VER, 0x200, PCI_ERR_SIZEOF, NULL);
+    if (rc) {
+        goto err_release_cdat;
+    }
+
     return;
 
+err_release_cdat:
+    cxl_doe_cdat_release(cxl_cstate);
+    g_free(regs->special_ops);
 err_address_space_free:
     address_space_destroy(&ct3d->hostmem_as);
     return;
@@ -465,6 +477,7 @@  static void ct3_exit(PCIDevice *pci_dev)
     CXLComponentState *cxl_cstate = &ct3d->cxl_cstate;
     ComponentRegisters *regs = &cxl_cstate->crb;
 
+    pcie_aer_exit(pci_dev);
     cxl_doe_cdat_release(cxl_cstate);
     g_free(regs->special_ops);
     address_space_destroy(&ct3d->hostmem_as);