| Message ID | 20230901012914.226527-4-gregory.price@memverge.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | CXL: SK hynix Niagara MHSLD Device | expand |
On Tue, Sep 05, 2023 at 10:59:15AM +0200, Philippe Mathieu-Daudé wrote: > Hi Gregory, > > On 1/9/23 03:29, Gregory Price wrote: > > For devices built on top of ct3, we need the init, realize, and > > exit functions exposed to correctly start up and tear down. > > You shouldn't need this. Your device class can inherit from > the CT3 base class by setting its .parent to TYPE_CXL_TYPE3: > realized this after the fact when testing and patching, forgot to remove it, good eye. Still learning QEMU internals. > > You can see some documentation about QOM here: > https://qemu-project.gitlab.io/qemu/devel/qom.html > But still you'll have to look at examples in the tree. > > Thanks! Gregory
Hi Gregory, On 1/9/23 03:29, Gregory Price wrote: > For devices built on top of ct3, we need the init, realize, and > exit functions exposed to correctly start up and tear down. You shouldn't need this. Your device class can inherit from the CT3 base class by setting its .parent to TYPE_CXL_TYPE3: static const TypeInfo my_cxl_types[] = { { .name = TYPE_MY_CXL_DEVICE_X, .parent = TYPE_CXL_TYPE3, .class_init = dev_x_class_init, }, { .name = TYPE_MY_CXL_DEVICE_Y, .parent = TYPE_CXL_TYPE3, .class_init = dev_y_class_init, } }; You can see some documentation about QOM here: https://qemu-project.gitlab.io/qemu/devel/qom.html But still you'll have to look at examples in the tree. > Signed-off-by: Gregory Price <gregory.price@memverge.com> > --- > hw/mem/cxl_type3.c | 8 ++++---- > include/hw/cxl/cxl_device.h | 5 +++++ > 2 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index 80d596ee10..a8d4a12f3e 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -950,7 +950,7 @@ static DOEProtocol doe_spdm_prot[] = { { } }; -static void ct3_realize(PCIDevice *pci_dev, Error **errp) +void ct3_realize(PCIDevice *pci_dev, Error **errp) { CXLType3Dev *ct3d = CXL_TYPE3(pci_dev); CXLComponentState *cxl_cstate = &ct3d->cxl_cstate; @@ -1054,7 +1054,7 @@ err_address_space_free: return; } -static void ct3_exit(PCIDevice *pci_dev) +void ct3_exit(PCIDevice *pci_dev) { CXLType3Dev *ct3d = CXL_TYPE3(pci_dev); CXLComponentState *cxl_cstate = &ct3d->cxl_cstate; @@ -1285,7 +1285,7 @@ MemTxResult cxl_type3_write(PCIDevice *d, hwaddr host_addr, uint64_t data, return address_space_write(as, dpa_offset, attrs, &data, size); } -static void ct3d_reset(DeviceState *dev) +void ct3d_reset(DeviceState *dev) { CXLType3Dev *ct3d = CXL_TYPE3(dev); uint32_t *reg_state = ct3d->cxl_cstate.crb.cache_mem_registers; @@ -2081,7 +2081,7 @@ void qmp_cxl_release_dynamic_capacity(const char *path, errp); } -static void ct3_class_init(ObjectClass *oc, void *data) +void ct3_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc); diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h index e824c5ade8..4ad38b689c 100644 --- a/include/hw/cxl/cxl_device.h +++ b/include/hw/cxl/cxl_device.h @@ -524,6 +524,11 @@ MemTxResult cxl_type3_read(PCIDevice *d, hwaddr host_addr, uint64_t *data, MemTxResult cxl_type3_write(PCIDevice *d, hwaddr host_addr, uint64_t data, unsigned size, MemTxAttrs attrs); +void ct3_realize(PCIDevice *pci_dev, Error **errp); +void ct3_exit(PCIDevice *pci_dev); +void ct3d_reset(DeviceState *d); +void ct3_class_init(ObjectClass *oc, void *data); + uint64_t cxl_device_get_timestamp(CXLDeviceState *cxlds); void cxl_event_init(CXLDeviceState *cxlds, int start_msg_num);
For devices built on top of ct3, we need the init, realize, and exit functions exposed to correctly start up and tear down. Signed-off-by: Gregory Price <gregory.price@memverge.com> --- hw/mem/cxl_type3.c | 8 ++++---- include/hw/cxl/cxl_device.h | 5 +++++ 2 files changed, 9 insertions(+), 4 deletions(-)