| Message ID | 20230905184406.135851-3-Benjamin.Cheatham@amd.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | CXL, ACPI, APEI, EINJ: Update EINJ for CXL 1.1 error types | expand |
Hi Ben,
kernel test robot noticed the following build warnings:
[auto build test WARNING on rafael-pm/linux-next]
[also build test WARNING on linus/master v6.5 next-20230905]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Ben-Cheatham/CXL-PCIE-Add-cxl_rcrb_addr-file-to-dport_dev/20230906-025405
base: https://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git linux-next
patch link: https://lore.kernel.org/r/20230905184406.135851-3-Benjamin.Cheatham%40amd.com
patch subject: [PATCH v3 2/3] ACPI, APEI, EINJ: Add CXL 1.1 EINJ error type support
config: alpha-allyesconfig (https://download.01.org/0day-ci/archive/20230906/202309060439.NyMjpqql-lkp@intel.com/config)
compiler: alpha-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20230906/202309060439.NyMjpqql-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202309060439.NyMjpqql-lkp@intel.com/
All warnings (new ones prefixed by >>):
In file included from drivers/cxl/cxl.h:11,
from drivers/cxl/cxlmem.h:9,
from drivers/cxl/core/port.c:11:
>> include/linux/cxl.h:12:19: warning: no previous prototype for 'cxl_find_rch_dport_by_rcrb' [-Wmissing-prototypes]
12 | struct cxl_dport *cxl_find_rch_dport_by_rcrb(resource_size_t rcrb_base)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/cxl/core/port.c:1125:19: error: redefinition of 'cxl_find_rch_dport_by_rcrb'
1125 | struct cxl_dport *cxl_find_rch_dport_by_rcrb(resource_size_t rcrb_base)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/cxl.h:12:19: note: previous definition of 'cxl_find_rch_dport_by_rcrb' with type 'struct cxl_dport *(resource_size_t)' {aka 'struct cxl_dport *(long long unsigned int)'}
12 | struct cxl_dport *cxl_find_rch_dport_by_rcrb(resource_size_t rcrb_base)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
--
In file included from drivers/cxl/cxl.h:11,
from drivers/cxl/cxlmem.h:9,
from drivers/cxl/core/pmem.c:6:
>> include/linux/cxl.h:12:19: warning: no previous prototype for 'cxl_find_rch_dport_by_rcrb' [-Wmissing-prototypes]
12 | struct cxl_dport *cxl_find_rch_dport_by_rcrb(resource_size_t rcrb_base)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
vim +/cxl_find_rch_dport_by_rcrb +12 include/linux/cxl.h
8
9 #if IS_ENABLED(CONFIG_CXL_ACPI)
10 struct cxl_dport *cxl_find_rch_dport_by_rcrb(resource_size_t rcrb_base);
11 #else
> 12 struct cxl_dport *cxl_find_rch_dport_by_rcrb(resource_size_t rcrb_base)
13 {
14 return NULL;
15 }
16 #endif
17
Hi Ben,
kernel test robot noticed the following build errors:
[auto build test ERROR on rafael-pm/linux-next]
[also build test ERROR on linus/master v6.5 next-20230905]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Ben-Cheatham/CXL-PCIE-Add-cxl_rcrb_addr-file-to-dport_dev/20230906-025405
base: https://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git linux-next
patch link: https://lore.kernel.org/r/20230905184406.135851-3-Benjamin.Cheatham%40amd.com
patch subject: [PATCH v3 2/3] ACPI, APEI, EINJ: Add CXL 1.1 EINJ error type support
config: alpha-allmodconfig (https://download.01.org/0day-ci/archive/20230906/202309061156.nyIdvSmV-lkp@intel.com/config)
compiler: alpha-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20230906/202309061156.nyIdvSmV-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202309061156.nyIdvSmV-lkp@intel.com/
All errors (new ones prefixed by >>):
alpha-linux-ld: drivers/cxl/security.o: in function `cxl_find_rch_dport_by_rcrb':
>> (.text+0x8d0): multiple definition of `cxl_find_rch_dport_by_rcrb'; drivers/cxl/pmem.o:(.text+0x1090): first defined here
diff --git a/drivers/acpi/apei/einj.c b/drivers/acpi/apei/einj.c index 013eb621dc92..0783ddd3ab4d 100644 --- a/drivers/acpi/apei/einj.c +++ b/drivers/acpi/apei/einj.c @@ -21,6 +21,7 @@ #include <linux/nmi.h> #include <linux/delay.h> #include <linux/mm.h> +#include <linux/cxl.h> #include <asm/unaligned.h> #include "apei-internal.h" @@ -36,6 +37,7 @@ #define MEM_ERROR_MASK (ACPI_EINJ_MEMORY_CORRECTABLE | \ ACPI_EINJ_MEMORY_UNCORRECTABLE | \ ACPI_EINJ_MEMORY_FATAL) +#define CXL_ERROR_MASK GENMASK(17, 12) /* * ACPI version 5 provides a SET_ERROR_TYPE_WITH_ADDRESS action. @@ -512,6 +514,24 @@ static int __einj_error_inject(u32 type, u32 flags, u64 param1, u64 param2, return rc; } +static int is_valid_cxl_addr(u64 addr) +{ + struct cxl_dport *dport; + + if (IS_REACHABLE(CONFIG_CXL_ACPI)) { + dport = cxl_find_rch_dport_by_rcrb((resource_size_t) addr); + + if (!IS_ERR_OR_NULL(dport)) + return 1; + } else { + pr_err("CONFIG_CXL_ACPI is not reachable.\n"); + return 0; + } + + pr_info("Could not find dport with rcrb 0x%llx\n", addr); + return 0; +} + /* Inject the specified hardware error */ static int einj_error_inject(u32 type, u32 flags, u64 param1, u64 param2, u64 param3, u64 param4) @@ -537,8 +557,11 @@ static int einj_error_inject(u32 type, u32 flags, u64 param1, u64 param2, if (type & ACPI5_VENDOR_BIT) { if (vendor_flags != SETWA_FLAGS_MEM) goto inject; - } else if (!(type & MEM_ERROR_MASK) && !(flags & SETWA_FLAGS_MEM)) + } else if (!(type & MEM_ERROR_MASK) && !(flags & SETWA_FLAGS_MEM)) { goto inject; + } else if (type & CXL_ERROR_MASK && is_valid_cxl_addr(param1)) { + goto inject; + } /* * Disallow crazy address masks that give BIOS leeway to pick @@ -807,3 +830,4 @@ module_exit(einj_exit); MODULE_AUTHOR("Huang Ying"); MODULE_DESCRIPTION("APEI Error INJection support"); MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS(CXL); diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index b69fd1c1d5d6..3961f099a775 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -1122,6 +1122,23 @@ struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port, } EXPORT_SYMBOL_NS_GPL(devm_cxl_add_rch_dport, CXL); +struct cxl_dport *cxl_find_rch_dport_by_rcrb(resource_size_t rcrb_base) +{ + struct cxl_dport *dport; + unsigned long index; + + if (!cxl_root) + return ERR_PTR(-ENODEV); + + xa_for_each(&cxl_root->dports, index, dport) + if ((dport->rch && dport->rcrb.base != CXL_RESOURCE_NONE) + && dport->rcrb.base == rcrb_base) + return dport; + + return NULL; +} +EXPORT_SYMBOL_NS_GPL(cxl_find_rch_dport_by_rcrb, CXL); + static int add_ep(struct cxl_ep *new) { struct cxl_port *port = new->dport->port; diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 4d5bce4bae7e..3e6779dbcd23 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -8,6 +8,7 @@ #include <linux/bitfield.h> #include <linux/bitops.h> #include <linux/log2.h> +#include <linux/cxl.h> #include <linux/io.h> /** diff --git a/include/linux/cxl.h b/include/linux/cxl.h new file mode 100644 index 000000000000..09889581d9f1 --- /dev/null +++ b/include/linux/cxl.h @@ -0,0 +1,18 @@ +#ifndef _LINUX_CXL_H +#define _LINUX_CXL_H + +#include <linux/xarray.h> +#include <linux/errno.h> + +struct cxl_dport; + +#if IS_ENABLED(CONFIG_CXL_ACPI) +struct cxl_dport *cxl_find_rch_dport_by_rcrb(resource_size_t rcrb_base); +#else +struct cxl_dport *cxl_find_rch_dport_by_rcrb(resource_size_t rcrb_base) +{ + return NULL; +} +#endif + +#endif
Add support for CXL EINJ error types for CXL 1.1 hosts added in ACPI v6.5. Because these error types target memory-mapped CXL 1.1 compliant downstream ports and not physical (normal/persistent) memory, these error types are not currently allowed through the memory range validation done by the EINJ driver. The MMIO address of a CXL 1.1 downstream port can be found in the cxl_rcrb_addr file in the corresponding dport directory under /sys/bus/cxl/devices/portX. CXL 1.1 error types follow the same procedure as a memory error type, but with param1 set to the downstream port MMIO address. Example usage: $ cd /sys/kernel/debug/apei/einj $ cat available_error_type 0x00000008 Memory Correctable 0x00000010 Memory Uncorrectable non-fatal 0x00000020 Memory Uncorrectable fatal 0x00000040 PCI Express Correctable 0x00000080 PCI Express Uncorrectable non-fatal 0x00000100 PCI Express Uncorrectable fatal 0x00008000 CXL.mem Protocol Correctable 0x00020000 CXL.mem Protocol Uncorrectable fatal $ echo 0x8000 > error_type $ echo 0xfffffffffffff000 > param2 $ echo 0x3 > flags $ cat /sys/bus/cxl/devices/portX/dportY/cxl_rcrb_addr 0xb2f00000 $ echo 0xb2f00000 > param1 $ echo 1 > error_inject Signed-off-by: Ben Cheatham <Benjamin.Cheatham@amd.com> --- drivers/acpi/apei/einj.c | 26 +++++++++++++++++++++++++- drivers/cxl/core/port.c | 17 +++++++++++++++++ drivers/cxl/cxl.h | 1 + include/linux/cxl.h | 18 ++++++++++++++++++ 4 files changed, 61 insertions(+), 1 deletion(-) create mode 100644 include/linux/cxl.h