| Message ID | 20240304194331.1586191-3-nifan.cxl@gmail.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Enabling DCD emulation support in Qemu | expand |
On Mon, 4 Mar 2024 11:33:57 -0800 nifan.cxl@gmail.com wrote: > From: Fan Ni <fan.ni@samsung.com> > > Per cxl spec r3.1, add dynamic capacity region representative based on > Table 8-165 and extend the cxl type3 device definition to include dc region > information. Also, based on info in 8.2.9.9.9.1, add 'Get Dynamic Capacity > Configuration' mailbox support. > > Note: we store region decode length as byte-wise length on the device, which > should be divided by 256 * MiB before being returned to the host > for "Get Dynamic Capacity Configuration" mailbox command per > specification. > > Signed-off-by: Fan Ni <fan.ni@samsung.com> Really minor nice to have type comments inline. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > --- > hw/cxl/cxl-mailbox-utils.c | 99 +++++++++++++++++++++++++++++++++++++ > include/hw/cxl/cxl_device.h | 16 ++++++ > 2 files changed, 115 insertions(+) > > diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c > index ba1d9901df..5792010c12 100644 > --- a/hw/cxl/cxl-mailbox-utils.c > +++ b/hw/cxl/cxl-mailbox-utils.c > @@ -22,6 +22,8 @@ > > #define CXL_CAPACITY_MULTIPLIER (256 * MiB) > #define CXL_DC_EVENT_LOG_SIZE 8 > +#define CXL_NUM_EXTENTS_SUPPORTED 512 > +#define CXL_NUM_TAGS_SUPPORTED 0 > > /* > * How to add a new command, example. The command set FOO, with cmd BAR. > @@ -80,6 +82,8 @@ enum { > #define GET_POISON_LIST 0x0 > #define INJECT_POISON 0x1 > #define CLEAR_POISON 0x2 > + DCD_CONFIG = 0x48, > + #define GET_DC_CONFIG 0x0 > PHYSICAL_SWITCH = 0x51, > #define IDENTIFY_SWITCH_DEVICE 0x0 > #define GET_PHYSICAL_PORT_STATE 0x1 > @@ -1238,6 +1242,91 @@ static CXLRetCode cmd_media_clear_poison(const struct cxl_cmd *cmd, > return CXL_MBOX_SUCCESS; > } > > +/* > + * CXL r3.1 section 8.2.9.9.9.1: Get Dynamic Capacity Configuration > + * (Opcode: 4800h) > + */ > +static CXLRetCode cmd_dcd_get_dyn_cap_config(const struct cxl_cmd *cmd, > + uint8_t *payload_in, > + size_t len_in, > + uint8_t *payload_out, > + size_t *len_out, > + CXLCCI *cci) > +{ > + CXLType3Dev *ct3d = CXL_TYPE3(cci->d); > + struct { > + uint8_t region_cnt; > + uint8_t start_region_id; > + } QEMU_PACKED *in; If you respin a few line breaks might help on readability. I'd stick one after each struct. > + struct { > + uint8_t num_regions; > + uint8_t regions_returned; > + uint8_t rsvd1[6]; > + struct { > + uint64_t base; > + uint64_t decode_len; > + uint64_t region_len; > + uint64_t block_size; > + uint32_t dsmadhandle; > + uint8_t flags; > + uint8_t rsvd2[3]; > + } QEMU_PACKED records[]; > + } QEMU_PACKED *out; } QEMU_PACKED *out = (void *)payload_out; (see below) > + struct { > + uint32_t num_extents_supported; > + uint32_t num_extents_available; > + uint32_t num_tags_supported; > + uint32_t num_tags_available; > + } QEMU_PACKED *extra_out; > + uint16_t record_count; > + uint16_t i; > + uint16_t out_pl_len; > + uint8_t start_region_id; > + > + in = (void *)payload_in; > + out = (void *)payload_out; These are a bit uninteresting so could just assign them at the definitions above? > + start_region_id = in->start_region_id; Perhaps something shorter like start_rid for the local variable? > + if (start_region_id >= ct3d->dc.num_regions) { > + return CXL_MBOX_INVALID_INPUT; > + } > + > + record_count = MIN(ct3d->dc.num_regions - in->start_region_id, > + in->region_cnt); I'd align with just after opening bracket. > + > + out_pl_len = sizeof(*out) + record_count * sizeof(out->records[0]); > + extra_out = (void *)(payload_out + out_pl_len); > + out_pl_len += sizeof(*extra_out); > + assert(out_pl_len <= CXL_MAILBOX_MAX_PAYLOAD_SIZE); > + > + out->num_regions = ct3d->dc.num_regions; > + out->regions_returned = record_count; > + for (i = 0; i < record_count; i++) { > + stq_le_p(&out->records[i].base, > + ct3d->dc.regions[start_region_id + i].base); > + stq_le_p(&out->records[i].decode_len, > + ct3d->dc.regions[start_region_id + i].decode_len / > + CXL_CAPACITY_MULTIPLIER); > + stq_le_p(&out->records[i].region_len, > + ct3d->dc.regions[start_region_id + i].len); > + stq_le_p(&out->records[i].block_size, > + ct3d->dc.regions[start_region_id + i].block_size); > + stl_le_p(&out->records[i].dsmadhandle, > + ct3d->dc.regions[start_region_id + i].dsmadhandle); > + out->records[i].flags = ct3d->dc.regions[start_region_id + i].flags; > + } > + /* > + * TODO: will assign proper values when extents and tags are introduced > + * to use. Drop the to use * TODO: Assign values once extents and tags are introduced. > + */ > + stl_le_p(&extra_out->num_extents_supported, CXL_NUM_EXTENTS_SUPPORTED); > + stl_le_p(&extra_out->num_extents_available, CXL_NUM_EXTENTS_SUPPORTED); > + stl_le_p(&extra_out->num_tags_supported, CXL_NUM_TAGS_SUPPORTED); > + stl_le_p(&extra_out->num_tags_available, CXL_NUM_TAGS_SUPPORTED); > + > + *len_out = out_pl_len; > + return CXL_MBOX_SUCCESS; > +}
diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c index ba1d9901df..5792010c12 100644 --- a/hw/cxl/cxl-mailbox-utils.c +++ b/hw/cxl/cxl-mailbox-utils.c @@ -22,6 +22,8 @@ #define CXL_CAPACITY_MULTIPLIER (256 * MiB) #define CXL_DC_EVENT_LOG_SIZE 8 +#define CXL_NUM_EXTENTS_SUPPORTED 512 +#define CXL_NUM_TAGS_SUPPORTED 0 /* * How to add a new command, example. The command set FOO, with cmd BAR. @@ -80,6 +82,8 @@ enum { #define GET_POISON_LIST 0x0 #define INJECT_POISON 0x1 #define CLEAR_POISON 0x2 + DCD_CONFIG = 0x48, + #define GET_DC_CONFIG 0x0 PHYSICAL_SWITCH = 0x51, #define IDENTIFY_SWITCH_DEVICE 0x0 #define GET_PHYSICAL_PORT_STATE 0x1 @@ -1238,6 +1242,91 @@ static CXLRetCode cmd_media_clear_poison(const struct cxl_cmd *cmd, return CXL_MBOX_SUCCESS; } +/* + * CXL r3.1 section 8.2.9.9.9.1: Get Dynamic Capacity Configuration + * (Opcode: 4800h) + */ +static CXLRetCode cmd_dcd_get_dyn_cap_config(const struct cxl_cmd *cmd, + uint8_t *payload_in, + size_t len_in, + uint8_t *payload_out, + size_t *len_out, + CXLCCI *cci) +{ + CXLType3Dev *ct3d = CXL_TYPE3(cci->d); + struct { + uint8_t region_cnt; + uint8_t start_region_id; + } QEMU_PACKED *in; + struct { + uint8_t num_regions; + uint8_t regions_returned; + uint8_t rsvd1[6]; + struct { + uint64_t base; + uint64_t decode_len; + uint64_t region_len; + uint64_t block_size; + uint32_t dsmadhandle; + uint8_t flags; + uint8_t rsvd2[3]; + } QEMU_PACKED records[]; + } QEMU_PACKED *out; + struct { + uint32_t num_extents_supported; + uint32_t num_extents_available; + uint32_t num_tags_supported; + uint32_t num_tags_available; + } QEMU_PACKED *extra_out; + uint16_t record_count; + uint16_t i; + uint16_t out_pl_len; + uint8_t start_region_id; + + in = (void *)payload_in; + out = (void *)payload_out; + start_region_id = in->start_region_id; + if (start_region_id >= ct3d->dc.num_regions) { + return CXL_MBOX_INVALID_INPUT; + } + + record_count = MIN(ct3d->dc.num_regions - in->start_region_id, + in->region_cnt); + + out_pl_len = sizeof(*out) + record_count * sizeof(out->records[0]); + extra_out = (void *)(payload_out + out_pl_len); + out_pl_len += sizeof(*extra_out); + assert(out_pl_len <= CXL_MAILBOX_MAX_PAYLOAD_SIZE); + + out->num_regions = ct3d->dc.num_regions; + out->regions_returned = record_count; + for (i = 0; i < record_count; i++) { + stq_le_p(&out->records[i].base, + ct3d->dc.regions[start_region_id + i].base); + stq_le_p(&out->records[i].decode_len, + ct3d->dc.regions[start_region_id + i].decode_len / + CXL_CAPACITY_MULTIPLIER); + stq_le_p(&out->records[i].region_len, + ct3d->dc.regions[start_region_id + i].len); + stq_le_p(&out->records[i].block_size, + ct3d->dc.regions[start_region_id + i].block_size); + stl_le_p(&out->records[i].dsmadhandle, + ct3d->dc.regions[start_region_id + i].dsmadhandle); + out->records[i].flags = ct3d->dc.regions[start_region_id + i].flags; + } + /* + * TODO: will assign proper values when extents and tags are introduced + * to use. + */ + stl_le_p(&extra_out->num_extents_supported, CXL_NUM_EXTENTS_SUPPORTED); + stl_le_p(&extra_out->num_extents_available, CXL_NUM_EXTENTS_SUPPORTED); + stl_le_p(&extra_out->num_tags_supported, CXL_NUM_TAGS_SUPPORTED); + stl_le_p(&extra_out->num_tags_available, CXL_NUM_TAGS_SUPPORTED); + + *len_out = out_pl_len; + return CXL_MBOX_SUCCESS; +} + #define IMMEDIATE_CONFIG_CHANGE (1 << 1) #define IMMEDIATE_DATA_CHANGE (1 << 2) #define IMMEDIATE_POLICY_CHANGE (1 << 3) @@ -1282,6 +1371,11 @@ static const struct cxl_cmd cxl_cmd_set[256][256] = { cmd_media_clear_poison, 72, 0 }, }; +static const struct cxl_cmd cxl_cmd_set_dcd[256][256] = { + [DCD_CONFIG][GET_DC_CONFIG] = { "DCD_GET_DC_CONFIG", + cmd_dcd_get_dyn_cap_config, 2, 0 }, +}; + static const struct cxl_cmd cxl_cmd_set_sw[256][256] = { [INFOSTAT][IS_IDENTIFY] = { "IDENTIFY", cmd_infostat_identify, 0, 0 }, [INFOSTAT][BACKGROUND_OPERATION_STATUS] = { "BACKGROUND_OPERATION_STATUS", @@ -1487,7 +1581,12 @@ void cxl_initialize_mailbox_swcci(CXLCCI *cci, DeviceState *intf, void cxl_initialize_mailbox_t3(CXLCCI *cci, DeviceState *d, size_t payload_max) { + CXLType3Dev *ct3d = CXL_TYPE3(d); + cxl_copy_cci_commands(cci, cxl_cmd_set); + if (ct3d->dc.num_regions) { + cxl_copy_cci_commands(cci, cxl_cmd_set_dcd); + } cci->d = d; /* No separation for PCI MB as protocol handled in PCI device */ diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h index 3cf3077afa..93ce047b28 100644 --- a/include/hw/cxl/cxl_device.h +++ b/include/hw/cxl/cxl_device.h @@ -422,6 +422,17 @@ typedef struct CXLPoison { typedef QLIST_HEAD(, CXLPoison) CXLPoisonList; #define CXL_POISON_LIST_LIMIT 256 +#define DCD_MAX_NUM_REGION 8 + +typedef struct CXLDCRegion { + uint64_t base; /* aligned to 256*MiB */ + uint64_t decode_len; /* aligned to 256*MiB */ + uint64_t len; + uint64_t block_size; + uint32_t dsmadhandle; + uint8_t flags; +} CXLDCRegion; + struct CXLType3Dev { /* Private */ PCIDevice parent_obj; @@ -454,6 +465,11 @@ struct CXLType3Dev { unsigned int poison_list_cnt; bool poison_list_overflowed; uint64_t poison_list_overflow_ts; + + struct dynamic_capacity { + uint8_t num_regions; /* 0-8 regions */ + CXLDCRegion regions[DCD_MAX_NUM_REGION]; + } dc; }; #define TYPE_CXL_TYPE3 "cxl-type3"