| Message ID | 20240307230432.2006490-1-dave.jiang@intel.com |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v4,1/3] cxl: Remove checking of iter in cxl_endpoint_get_perf_coordinates() | expand |
On Thu, 07 Mar 2024, Dave Jiang wrote: >The while() loop in cxl_endpoint_get_perf_coordinates() checks to see if >'iter' is valid as part of the condition breaking out of the loop. However, >iter is being used before the check at the end of the while loop before >the next iteration starts. Given that the loop doesn't expect the iter to >be NULL because it stops before the root port, remove the iter check. > >The presence of the iter or removing the iter does not impact the behavior >of the code. This is a code clean up and not a bug fix. > For the whole series: Reviewed-by: Davidlohr Bueso <dave@stgolabs.net> >Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> >Signed-off-by: Dave Jiang <dave.jiang@intel.com> >--- > drivers/cxl/core/port.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > >diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c >index e59d9d37aa65..e1d30a885700 100644 >--- a/drivers/cxl/core/port.c >+++ b/drivers/cxl/core/port.c >@@ -2142,7 +2142,7 @@ int cxl_endpoint_get_perf_coordinates(struct cxl_port *port, > * port each iteration. If the parent is cxl root then there is > * nothing to gather. > */ >- while (iter && !is_cxl_root(to_cxl_port(iter->dev.parent))) { >+ while (!is_cxl_root(to_cxl_port(iter->dev.parent))) { > combine_coordinates(&c, &dport->sw_coord); > c.write_latency += dport->link_latency; > c.read_latency += dport->link_latency; >-- >2.44.0 >
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index e59d9d37aa65..e1d30a885700 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -2142,7 +2142,7 @@ int cxl_endpoint_get_perf_coordinates(struct cxl_port *port, * port each iteration. If the parent is cxl root then there is * nothing to gather. */ - while (iter && !is_cxl_root(to_cxl_port(iter->dev.parent))) { + while (!is_cxl_root(to_cxl_port(iter->dev.parent))) { combine_coordinates(&c, &dport->sw_coord); c.write_latency += dport->link_latency; c.read_latency += dport->link_latency;