diff mbox series

[v3] cxl: Fix use of phys_to_target_node() for x86

Message ID 20240424154756.2152614-1-rrichter@amd.com
State Accepted
Commit 866c0674541f81a85fd592990f373f560bb23e8a
Headers show
Series [v3] cxl: Fix use of phys_to_target_node() for x86 | expand

Commit Message

Robert Richter April 24, 2024, 3:47 p.m. UTC 
The CXL driver uses both functions phys_to_target_node() and
memory_add_physaddr_to_nid(). The x86 architecture relies on the
NUMA_KEEP_MEMINFO kernel option enabled for both functions to work
correct. Update Kconfig to make sure the option is always enabled for
the driver.

Suggested-by: Dan Williams <dan.j.williams@intel.com>
Link: http://lore.kernel.org/r/65f8b191c0422_aa222941b@dwillia2-mobl3.amr.corp.intel.com.notmuch
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Robert Richter <rrichter@amd.com>
---
V3: updated SOB chain
---
 drivers/cxl/Kconfig | 1 +
 1 file changed, 1 insertion(+)

Comments

Davidlohr Bueso April 24, 2024, 11:11 p.m. UTC | #1 
On Wed, 24 Apr 2024, Robert Richter wrote:

>The CXL driver uses both functions phys_to_target_node() and
>memory_add_physaddr_to_nid(). The x86 architecture relies on the
>NUMA_KEEP_MEMINFO kernel option enabled for both functions to work
>correct. Update Kconfig to make sure the option is always enabled for
>the driver.
>
>Suggested-by: Dan Williams <dan.j.williams@intel.com>
>Link: http://lore.kernel.org/r/65f8b191c0422_aa222941b@dwillia2-mobl3.amr.corp.intel.com.notmuch
>Reviewed-by: Ira Weiny <ira.weiny@intel.com>
>Reviewed-by: Dan Williams <dan.j.williams@intel.com>
>Signed-off-by: Robert Richter <rrichter@amd.com>

Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>
diff mbox series

Patch

diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig
index 67998dbd1d46..6140b3529a29 100644
--- a/drivers/cxl/Kconfig
+++ b/drivers/cxl/Kconfig
@@ -6,6 +6,7 @@  menuconfig CXL_BUS
 	select FW_UPLOAD
 	select PCI_DOE
 	select FIRMWARE_TABLE
+	select NUMA_KEEP_MEMINFO if (NUMA && X86)
 	help
 	  CXL is a bus that is electrically compatible with PCI Express, but
 	  layers three protocols on that signalling (CXL.io, CXL.cache, and