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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C Received: from SATLEXMB03.amd.com (165.204.84.17) by BN2PEPF000044A9.mail.protection.outlook.com (10.167.243.103) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7587.21 via Frontend Transport; Thu, 16 May 2024 08:12:19 +0000 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 16 May 2024 03:12:18 -0500 Received: from xcbalucerop41x.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35 via Frontend Transport; Thu, 16 May 2024 03:12:17 -0500 From: To: , , , , CC: Alejandro Lucero Subject: [RFC PATCH 02/13] cxl: add type2 device basic support Date: Thu, 16 May 2024 09:11:51 +0100 Message-ID: <20240516081202.27023-3-alucerop@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240516081202.27023-1-alucerop@amd.com> References: <20240516081202.27023-1-alucerop@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Received-SPF: None (SATLEXMB03.amd.com: alucerop@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A9:EE_|DM6PR12MB4170:EE_ X-MS-Office365-Filtering-Correlation-Id: b14c2c3d-d01f-49cc-f11a-08dc757fe815 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|376005|36860700004|1800799015|82310400017; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 May 2024 08:12:19.4191 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b14c2c3d-d01f-49cc-f11a-08dc757fe815 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A9.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4170 From: Alejandro Lucero Differientiating Type3, aka memory expanders, from Type2, aka device accelerators, with a new function for initializing cxl_dev_state. Adding a type2 driver for a CXL emulated device inside CXL kernel testing infrastructure as a client for the functionality added. Signed-off-by: Alejandro Lucero Signed-off-by: Dan Williams Signed-off-by: Alejandro Lucero --- drivers/cxl/core/memdev.c | 15 ++++++ include/linux/cxlmem.h | 2 + tools/testing/cxl/Kbuild | 1 + tools/testing/cxl/type2/Kbuild | 7 +++ tools/testing/cxl/type2/pci_type2.c | 80 +++++++++++++++++++++++++++++ 5 files changed, 105 insertions(+) create mode 100644 tools/testing/cxl/type2/Kbuild create mode 100644 tools/testing/cxl/type2/pci_type2.c diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c index 07cd0b8b026f..0336b3f14f4a 100644 --- a/drivers/cxl/core/memdev.c +++ b/drivers/cxl/core/memdev.c @@ -659,6 +659,21 @@ static void detach_memdev(struct work_struct *work) static struct lock_class_key cxl_memdev_key; +struct cxl_dev_state *cxl_accel_state_create(struct device *dev) +{ + struct cxl_dev_state *cxlds; + + cxlds = devm_kzalloc(dev, sizeof(*cxlds), GFP_KERNEL); + if (!cxlds) + return ERR_PTR(-ENOMEM); + + cxlds->dev = dev; + cxlds->type = CXL_DEVTYPE_DEVMEM; + + return cxlds; +} +EXPORT_SYMBOL_NS_GPL(cxl_accel_state_create, CXL); + static struct cxl_memdev *cxl_memdev_alloc(struct cxl_dev_state *cxlds, const struct file_operations *fops) { diff --git a/include/linux/cxlmem.h b/include/linux/cxlmem.h index 0d26a45a4af2..e8d12b543db1 100644 --- a/include/linux/cxlmem.h +++ b/include/linux/cxlmem.h @@ -859,4 +859,6 @@ struct cxl_hdm { struct seq_file; struct dentry *cxl_debugfs_create_dir(const char *dir); void cxl_dpa_debug(struct seq_file *file, struct cxl_dev_state *cxlds); + +struct cxl_dev_state *cxl_accel_state_create(struct device *dev); #endif /* __CXL_MEM_H__ */ diff --git a/tools/testing/cxl/Kbuild b/tools/testing/cxl/Kbuild index 030b388800f0..a285719c4db6 100644 --- a/tools/testing/cxl/Kbuild +++ b/tools/testing/cxl/Kbuild @@ -69,3 +69,4 @@ cxl_core-y += cxl_core_exports.o KBUILD_CFLAGS := $(filter-out -Wmissing-prototypes -Wmissing-declarations, $(KBUILD_CFLAGS)) obj-m += test/ +obj-m += type2/ diff --git a/tools/testing/cxl/type2/Kbuild b/tools/testing/cxl/type2/Kbuild new file mode 100644 index 000000000000..a96ad4d64924 --- /dev/null +++ b/tools/testing/cxl/type2/Kbuild @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-m += pci_type2.o + +cxl_pci_type2-y := cxl_pci_type2.o + +KBUILD_CFLAGS := $(filter-out -Wmissing-prototypes -Wmissing-declarations, $(KBUILD_CFLAGS)) diff --git a/tools/testing/cxl/type2/pci_type2.c b/tools/testing/cxl/type2/pci_type2.c new file mode 100644 index 000000000000..863ce7dc28ef --- /dev/null +++ b/tools/testing/cxl/type2/pci_type2.c @@ -0,0 +1,80 @@ +#include +#include +#include +#include +#include + +struct cxl_dev_state *cxlds; + +#define CXL_TYPE2_MEM_SIZE (1024*1024*256) + +static int type2_pci_probe(struct pci_dev *pci_dev, + const struct pci_device_id *entry) + +{ + u16 dvsec; + + dvsec = pci_find_dvsec_capability(pci_dev, PCI_DVSEC_VENDOR_ID_CXL, CXL_DVSEC_PCIE_DEVICE); + + if (!dvsec) { + pci_info(pci_dev, "No CXL capability (vendor: %x\n", pci_dev->vendor); + return 0; + } else { + pci_info(pci_dev, "CXL CXL_DVSEC_PCIE_DEVICE capability found"); + } + + cxlds = cxl_accel_state_create(&pci_dev->dev); + if (IS_ERR(cxlds)) + return PTR_ERR(cxlds); + + pci_info(pci_dev, "Initializing cxlds..."); + cxlds->cxl_dvsec = dvsec; + cxlds->serial = pci_dev->dev.id; + + /* Should not this be based on DVSEC range size registers */ + cxlds->dpa_res = DEFINE_RES_MEM(0, CXL_TYPE2_MEM_SIZE); + cxlds->ram_res = DEFINE_RES_MEM_NAMED(0, CXL_TYPE2_MEM_SIZE, "ram"); + + return 0; +} + +static void type2_pci_remove(struct pci_dev *pci_dev) +{ + +} + +/* PCI device ID table */ +static const struct pci_device_id type2_pci_table[] = { + {PCI_DEVICE(PCI_VENDOR_ID_AMD, 0xbabe)}, + {0} /* end of list */ +}; + +static struct pci_driver type2_pci_driver = { + .name = KBUILD_MODNAME, + .id_table = type2_pci_table, + .probe = type2_pci_probe, + .remove = type2_pci_remove, +}; + +static int __init type2_cxl_init(void) +{ + int rc; + + rc = pci_register_driver(&type2_pci_driver); + + return rc; +} + +static void __exit type2_cxl_exit(void) +{ + pci_unregister_driver(&type2_pci_driver); +} + +module_init(type2_cxl_init); +module_exit(type2_cxl_exit); + +MODULE_AUTHOR("Alejadro Lucero "); +MODULE_DESCRIPTION("CXL Type2 device support, driver test"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS(CXL); +MODULE_DEVICE_TABLE(pci, type2_pci_table);