| Message ID | 20240516081202.27023-9-alucerop@amd.com |
|---|---|
| State | New, archived |
| Headers | show |
| Series | RFC: add Type2 device support | expand |
From: Alejandro Lucero <alucerop@amd.com> Based on the requirements from the endpoint and the topology such an endpoint is attached to, this function informs about maximum host physical address space possible to request. This is not a reservation but only information which could change at the point the request based on this information is made. Based on: https://lore.kernel.org/linux-cxl/168592149709.1948938.8663425987110396027.stgit@dwillia2-xfh.jf.intel.com/T/#m6fbe775541da3cd477d65fa95c8acdc347345b4f Signed-off-by: Alejandro Lucero <alucerop@amd.com> Co-developed-by: Dan Williams <dan.j.williams@intel.com> On 5/16/24 09:11, alucerop@amd.com wrote: > From: Alejandro Lucero <alucerop@amd.com> > > Based on the requirements from the endpoint and the topology such an > endpoint is attached to, this function informs about maximum host > physical address space possible to request. This is not a reservation > but only information which could change at the point the request based > on this information is made. > > Signed-off-by: Alejandro Lucero <alucerop@amd.com> > Signed-off-by: Dan Williams <dan.j.williams@intel.com> > --- > drivers/cxl/core/region.c | 163 ++++++++++++++++++++++++++++ > include/linux/cxl.h | 5 + > include/linux/cxlmem.h | 5 + > tools/testing/cxl/type2/pci_type2.c | 23 +++- > 4 files changed, 195 insertions(+), 1 deletion(-) > > diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c > index 70e86a7c241d..2731fd4243a1 100644 > --- a/drivers/cxl/core/region.c > +++ b/drivers/cxl/core/region.c > @@ -702,6 +702,169 @@ static int free_hpa(struct cxl_region *cxlr) > return 0; > } > > + > +struct cxlrd_max_context { > + struct device * const *host_bridges; > + int interleave_ways; > + unsigned long flags; > + resource_size_t max_hpa; > + struct cxl_root_decoder *cxlrd; > +}; > + > +static int find_max_hpa(struct device *dev, void *data) > +{ > + struct cxlrd_max_context *ctx = data; > + struct cxl_switch_decoder *cxlsd; > + struct cxl_root_decoder *cxlrd; > + struct resource *res, *prev; > + struct cxl_decoder *cxld; > + resource_size_t max; > + int found; > + > + if (!is_root_decoder(dev)) > + return 0; > + > + cxlrd = to_cxl_root_decoder(dev); > + cxld = &cxlrd->cxlsd.cxld; > + if ((cxld->flags & ctx->flags) != ctx->flags) { > + dev_dbg(dev, "find_max_hpa, flags not matching: %08lx vs %08lx\n", > + cxld->flags, ctx->flags); > + return 0; > + } > + > + /* A Host bridge could have more interleave ways than an > + * endpoint, couldn´t it? > + * > + * What does interleave ways mean here in terms of the requestor? > + * Why the FFMWS has 0 interleave ways but root port has 1? > + */ > + if (cxld->interleave_ways != ctx->interleave_ways) { > + dev_dbg(dev, "find_max_hpa, interleave_ways not matching\n"); > + return 0; > + } > + > + cxlsd = &cxlrd->cxlsd; > + > + guard(rwsem_read)(&cxl_region_rwsem); > + found = 0; > + for (int i = 0; i < ctx->interleave_ways; i++) > + for (int j = 0; j < ctx->interleave_ways; j++) > + if (ctx->host_bridges[i] == > + cxlsd->target[j]->dport_dev) { > + found++; > + break; > + } > + > + if (found != ctx->interleave_ways) { > + dev_dbg(dev, "find_max_hpa, no interleave_ways found\n"); > + return 0; > + } > + > + /* > + * Walk the root decoder resource range relying on cxl_region_rwsem to > + * preclude sibling arrival/departure and find the largest free space > + * gap. > + */ > + lockdep_assert_held_read(&cxl_region_rwsem); > + max = 0; > + res = cxlrd->res->child; > + if (!res) > + max = resource_size(cxlrd->res); > + else > + max = 0; > + > + for (prev = NULL; res; prev = res, res = res->sibling) { > + struct resource *next = res->sibling; > + resource_size_t free = 0; > + > + if (!prev && res->start > cxlrd->res->start) { > + free = res->start - cxlrd->res->start; > + max = max(free, max); > + } > + if (prev && res->start > prev->end + 1) { > + free = res->start - prev->end + 1; > + max = max(free, max); > + } > + if (next && res->end + 1 < next->start) { > + free = next->start - res->end + 1; > + max = max(free, max); > + } > + if (!next && res->end + 1 < cxlrd->res->end + 1) { > + free = cxlrd->res->end + 1 - res->end + 1; > + max = max(free, max); > + } > + } > + > + if (max > ctx->max_hpa) { > + if (ctx->cxlrd) > + put_device(CXLRD_DEV(ctx->cxlrd)); > + get_device(CXLRD_DEV(cxlrd)); > + ctx->cxlrd = cxlrd; > + ctx->max_hpa = max; > + dev_info(CXLRD_DEV(cxlrd), "found %pa bytes of free space\n", &max); > + } > + return 0; > +} > + > +/** > + * cxl_get_hpa_freespace - find a root decoder with free capacity per constraints > + * @endpoint: an endpoint that is mapped by the returned decoder > + * @host_bridges: array of host-bridges that the decoder must interleave > + * @interleave_ways: number of entries in @host_bridges > + * @flags: CXL_DECODER_F flags for selecting RAM vs PMEM, and HDM-H vs HDM-D[B] > + * @max: output parameter of bytes available in the returned decoder > + * > + * The return tuple of a 'struct cxl_root_decoder' and 'bytes available (@max)' > + * is a point in time snapshot. If by the time the caller goes to use this root > + * decoder's capacity the capacity is reduced then caller needs to loop and > + * retry. > + * > + * The returned root decoder has an elevated reference count that needs to be > + * put with put_device(cxlrd_dev(cxlrd)). Locking context is with > + * cxl_{acquire,release}_endpoint(), that ensures removal of the root decoder > + * does not race. > + */ > +struct cxl_root_decoder *cxl_get_hpa_freespace(struct cxl_port *endpoint, > + struct device *const *host_bridges, > + int interleave_ways, > + unsigned long flags, > + resource_size_t *max) > +{ > + > + struct cxlrd_max_context ctx = { > + .host_bridges = host_bridges, > + .interleave_ways = interleave_ways, > + .flags = flags, > + }; > + struct cxl_port *root_port; > + struct cxl_root *root; > + > + if (!is_cxl_endpoint(endpoint)) { > + dev_dbg(&endpoint->dev, "hpa requestor is not an endpointr\n"); > + return ERR_PTR(-EINVAL); > + } > + > + root = find_cxl_root(endpoint); > + if (!root) { > + dev_dbg(&endpoint->dev, "endpoint can not be related to a root port\n"); > + return ERR_PTR(-ENXIO); > + } > + > + root_port = &root->port; > + down_read(&cxl_region_rwsem); > + device_for_each_child(&root_port->dev, &ctx, find_max_hpa); > + up_read(&cxl_region_rwsem); > + put_device(&root_port->dev); > + > + if (!ctx.cxlrd) > + return ERR_PTR(-ENOMEM); > + > + *max = ctx.max_hpa; > + return ctx.cxlrd; > +} > +EXPORT_SYMBOL_NS_GPL(cxl_get_hpa_freespace, CXL); > + > + > static ssize_t size_store(struct device *dev, struct device_attribute *attr, > const char *buf, size_t len) > { > diff --git a/include/linux/cxl.h b/include/linux/cxl.h > index 036d17db68e0..1b2377062693 100644 > --- a/include/linux/cxl.h > +++ b/include/linux/cxl.h > @@ -766,6 +766,11 @@ struct cxl_decoder *to_cxl_decoder(struct device *dev); > struct cxl_root_decoder *to_cxl_root_decoder(struct device *dev); > struct cxl_switch_decoder *to_cxl_switch_decoder(struct device *dev); > struct cxl_endpoint_decoder *to_cxl_endpoint_decoder(struct device *dev); > + > +#define CXLED_DEV(cxled) &cxled->cxld.dev > + > +#define CXLRD_DEV(cxlrd) &cxlrd->cxlsd.cxld.dev > + > bool is_root_decoder(struct device *dev); > bool is_switch_decoder(struct device *dev); > bool is_endpoint_decoder(struct device *dev); > diff --git a/include/linux/cxlmem.h b/include/linux/cxlmem.h > index 11fe8367b046..342ccd5486d3 100644 > --- a/include/linux/cxlmem.h > +++ b/include/linux/cxlmem.h > @@ -865,4 +865,9 @@ struct dentry *cxl_debugfs_create_dir(const char *dir); > void cxl_dpa_debug(struct seq_file *file, struct cxl_dev_state *cxlds); > > struct cxl_dev_state *cxl_accel_state_create(struct device *dev); > +struct cxl_root_decoder *cxl_get_hpa_freespace(struct cxl_port *endpoint, > + struct device *const *host_bridges, > + int interleave_ways, > + unsigned long flags, > + resource_size_t *max); > #endif /* __CXL_MEM_H__ */ > diff --git a/tools/testing/cxl/type2/pci_type2.c b/tools/testing/cxl/type2/pci_type2.c > index 948cc95c5780..deb5eeae501b 100644 > --- a/tools/testing/cxl/type2/pci_type2.c > +++ b/tools/testing/cxl/type2/pci_type2.c > @@ -4,6 +4,7 @@ > #include <linux/cxlpci.h> > #include <linux/cxlmem.h> > > +struct cxl_root_decoder *cxlrd; > struct cxl_dev_state *cxlds; > struct cxl_memdev *cxlmd; > struct cxl_port *endpoint; > @@ -15,6 +16,7 @@ static int type2_pci_probe(struct pci_dev *pci_dev, > > { > struct cxl_register_map map; > + resource_size_t max = 0; > u16 dvsec; > int rc; > > @@ -79,9 +81,28 @@ static int type2_pci_probe(struct pci_dev *pci_dev, > return PTR_ERR(endpoint); > } > > + pci_info(pci_dev, "cxl hpa_freespace..."); > + cxlrd = cxl_get_hpa_freespace(endpoint, &endpoint->host_bridge, 1, > + CXL_DECODER_F_RAM | CXL_DECODER_F_TYPE2, > + &max); > + > + if (IS_ERR(cxlrd)) { > + dev_dbg(&pci_dev->dev, "cxl_get_hpa_freespace failed\n"); > + rc = PTR_ERR(cxlrd); > + goto out; > + } > + > + if (max < CXL_TYPE2_MEM_SIZE) { > + dev_dbg(&pci_dev->dev, "%s: no enough free HPA space %llu < %u\n", > + __func__, max, CXL_TYPE2_MEM_SIZE); > + rc = -ENOMEM; > + goto out; > + } > + > +out: > cxl_release_endpoint(cxlmd, endpoint); > > - return 0; > + return rc; > } > > static void type2_pci_remove(struct pci_dev *pci_dev)
diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index 70e86a7c241d..2731fd4243a1 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -702,6 +702,169 @@ static int free_hpa(struct cxl_region *cxlr) return 0; } + +struct cxlrd_max_context { + struct device * const *host_bridges; + int interleave_ways; + unsigned long flags; + resource_size_t max_hpa; + struct cxl_root_decoder *cxlrd; +}; + +static int find_max_hpa(struct device *dev, void *data) +{ + struct cxlrd_max_context *ctx = data; + struct cxl_switch_decoder *cxlsd; + struct cxl_root_decoder *cxlrd; + struct resource *res, *prev; + struct cxl_decoder *cxld; + resource_size_t max; + int found; + + if (!is_root_decoder(dev)) + return 0; + + cxlrd = to_cxl_root_decoder(dev); + cxld = &cxlrd->cxlsd.cxld; + if ((cxld->flags & ctx->flags) != ctx->flags) { + dev_dbg(dev, "find_max_hpa, flags not matching: %08lx vs %08lx\n", + cxld->flags, ctx->flags); + return 0; + } + + /* A Host bridge could have more interleave ways than an + * endpoint, couldn´t it? + * + * What does interleave ways mean here in terms of the requestor? + * Why the FFMWS has 0 interleave ways but root port has 1? + */ + if (cxld->interleave_ways != ctx->interleave_ways) { + dev_dbg(dev, "find_max_hpa, interleave_ways not matching\n"); + return 0; + } + + cxlsd = &cxlrd->cxlsd; + + guard(rwsem_read)(&cxl_region_rwsem); + found = 0; + for (int i = 0; i < ctx->interleave_ways; i++) + for (int j = 0; j < ctx->interleave_ways; j++) + if (ctx->host_bridges[i] == + cxlsd->target[j]->dport_dev) { + found++; + break; + } + + if (found != ctx->interleave_ways) { + dev_dbg(dev, "find_max_hpa, no interleave_ways found\n"); + return 0; + } + + /* + * Walk the root decoder resource range relying on cxl_region_rwsem to + * preclude sibling arrival/departure and find the largest free space + * gap. + */ + lockdep_assert_held_read(&cxl_region_rwsem); + max = 0; + res = cxlrd->res->child; + if (!res) + max = resource_size(cxlrd->res); + else + max = 0; + + for (prev = NULL; res; prev = res, res = res->sibling) { + struct resource *next = res->sibling; + resource_size_t free = 0; + + if (!prev && res->start > cxlrd->res->start) { + free = res->start - cxlrd->res->start; + max = max(free, max); + } + if (prev && res->start > prev->end + 1) { + free = res->start - prev->end + 1; + max = max(free, max); + } + if (next && res->end + 1 < next->start) { + free = next->start - res->end + 1; + max = max(free, max); + } + if (!next && res->end + 1 < cxlrd->res->end + 1) { + free = cxlrd->res->end + 1 - res->end + 1; + max = max(free, max); + } + } + + if (max > ctx->max_hpa) { + if (ctx->cxlrd) + put_device(CXLRD_DEV(ctx->cxlrd)); + get_device(CXLRD_DEV(cxlrd)); + ctx->cxlrd = cxlrd; + ctx->max_hpa = max; + dev_info(CXLRD_DEV(cxlrd), "found %pa bytes of free space\n", &max); + } + return 0; +} + +/** + * cxl_get_hpa_freespace - find a root decoder with free capacity per constraints + * @endpoint: an endpoint that is mapped by the returned decoder + * @host_bridges: array of host-bridges that the decoder must interleave + * @interleave_ways: number of entries in @host_bridges + * @flags: CXL_DECODER_F flags for selecting RAM vs PMEM, and HDM-H vs HDM-D[B] + * @max: output parameter of bytes available in the returned decoder + * + * The return tuple of a 'struct cxl_root_decoder' and 'bytes available (@max)' + * is a point in time snapshot. If by the time the caller goes to use this root + * decoder's capacity the capacity is reduced then caller needs to loop and + * retry. + * + * The returned root decoder has an elevated reference count that needs to be + * put with put_device(cxlrd_dev(cxlrd)). Locking context is with + * cxl_{acquire,release}_endpoint(), that ensures removal of the root decoder + * does not race. + */ +struct cxl_root_decoder *cxl_get_hpa_freespace(struct cxl_port *endpoint, + struct device *const *host_bridges, + int interleave_ways, + unsigned long flags, + resource_size_t *max) +{ + + struct cxlrd_max_context ctx = { + .host_bridges = host_bridges, + .interleave_ways = interleave_ways, + .flags = flags, + }; + struct cxl_port *root_port; + struct cxl_root *root; + + if (!is_cxl_endpoint(endpoint)) { + dev_dbg(&endpoint->dev, "hpa requestor is not an endpointr\n"); + return ERR_PTR(-EINVAL); + } + + root = find_cxl_root(endpoint); + if (!root) { + dev_dbg(&endpoint->dev, "endpoint can not be related to a root port\n"); + return ERR_PTR(-ENXIO); + } + + root_port = &root->port; + down_read(&cxl_region_rwsem); + device_for_each_child(&root_port->dev, &ctx, find_max_hpa); + up_read(&cxl_region_rwsem); + put_device(&root_port->dev); + + if (!ctx.cxlrd) + return ERR_PTR(-ENOMEM); + + *max = ctx.max_hpa; + return ctx.cxlrd; +} +EXPORT_SYMBOL_NS_GPL(cxl_get_hpa_freespace, CXL); + + static ssize_t size_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t len) { diff --git a/include/linux/cxl.h b/include/linux/cxl.h index 036d17db68e0..1b2377062693 100644 --- a/include/linux/cxl.h +++ b/include/linux/cxl.h @@ -766,6 +766,11 @@ struct cxl_decoder *to_cxl_decoder(struct device *dev); struct cxl_root_decoder *to_cxl_root_decoder(struct device *dev); struct cxl_switch_decoder *to_cxl_switch_decoder(struct device *dev); struct cxl_endpoint_decoder *to_cxl_endpoint_decoder(struct device *dev); + +#define CXLED_DEV(cxled) &cxled->cxld.dev + +#define CXLRD_DEV(cxlrd) &cxlrd->cxlsd.cxld.dev + bool is_root_decoder(struct device *dev); bool is_switch_decoder(struct device *dev); bool is_endpoint_decoder(struct device *dev); diff --git a/include/linux/cxlmem.h b/include/linux/cxlmem.h index 11fe8367b046..342ccd5486d3 100644 --- a/include/linux/cxlmem.h +++ b/include/linux/cxlmem.h @@ -865,4 +865,9 @@ struct dentry *cxl_debugfs_create_dir(const char *dir); void cxl_dpa_debug(struct seq_file *file, struct cxl_dev_state *cxlds); struct cxl_dev_state *cxl_accel_state_create(struct device *dev); +struct cxl_root_decoder *cxl_get_hpa_freespace(struct cxl_port *endpoint, + struct device *const *host_bridges, + int interleave_ways, + unsigned long flags, + resource_size_t *max); #endif /* __CXL_MEM_H__ */ diff --git a/tools/testing/cxl/type2/pci_type2.c b/tools/testing/cxl/type2/pci_type2.c index 948cc95c5780..deb5eeae501b 100644 --- a/tools/testing/cxl/type2/pci_type2.c +++ b/tools/testing/cxl/type2/pci_type2.c @@ -4,6 +4,7 @@ #include <linux/cxlpci.h> #include <linux/cxlmem.h> +struct cxl_root_decoder *cxlrd; struct cxl_dev_state *cxlds; struct cxl_memdev *cxlmd; struct cxl_port *endpoint; @@ -15,6 +16,7 @@ static int type2_pci_probe(struct pci_dev *pci_dev, { struct cxl_register_map map; + resource_size_t max = 0; u16 dvsec; int rc; @@ -79,9 +81,28 @@ static int type2_pci_probe(struct pci_dev *pci_dev, return PTR_ERR(endpoint); } + pci_info(pci_dev, "cxl hpa_freespace..."); + cxlrd = cxl_get_hpa_freespace(endpoint, &endpoint->host_bridge, 1, + CXL_DECODER_F_RAM | CXL_DECODER_F_TYPE2, + &max); + + if (IS_ERR(cxlrd)) { + dev_dbg(&pci_dev->dev, "cxl_get_hpa_freespace failed\n"); + rc = PTR_ERR(cxlrd); + goto out; + } + + if (max < CXL_TYPE2_MEM_SIZE) { + dev_dbg(&pci_dev->dev, "%s: no enough free HPA space %llu < %u\n", + __func__, max, CXL_TYPE2_MEM_SIZE); + rc = -ENOMEM; + goto out; + } + +out: cxl_release_endpoint(cxlmd, endpoint); - return 0; + return rc; } static void type2_pci_remove(struct pci_dev *pci_dev)