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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1PEPF000066ED.mail.protection.outlook.com (10.167.249.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7677.15 via Frontend Transport; Mon, 17 Jun 2024 20:06:04 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 17 Jun 2024 15:06:03 -0500 From: Terry Bowman To: , , , , , , , , , , , , , , , Subject: [RFC PATCH 9/9] cxl/pci: Enable interrupts for CXL PCIe ports' AER internal errors Date: Mon, 17 Jun 2024 15:04:11 -0500 Message-ID: <20240617200411.1426554-10-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240617200411.1426554-1-terry.bowman@amd.com> References: <20240617200411.1426554-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000066ED:EE_|DS0PR12MB8453:EE_ X-MS-Office365-Filtering-Correlation-Id: bf1ae36e-3097-488e-9f0f-08dc8f08eadc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230037|7416011|376011|36860700010|1800799021|82310400023|921017; X-Microsoft-Antispam-Message-Info: U8iCPKh2nNwoqVLMzpirLYCl+Q+TeRDT5HURUMePdoG3wj4hIWWfVQyJTZEbz6Ae/uRzj/V6ItMv9TfCJY1ZaW/wHHrrXsllpcQ19bJWYTAJQ/qx62xrPshosA0iMXvQ49nzb49iW/kOga6XRT+fYSW/E9S/NZtsTxBjI+id9pEyHBKhYRXom5NN/ZlHTrGN9lmmvKZPysTReImFH+tjzPAmhRmUOTlzFmbW2gtsESXxZhiVr3pA5tBQWCeVfW+1BjajgNASIiV+7dG4RSPxz8fgAe8TlqiK+TfSM7RaULUUSnuuU5u5yPrc3QAB0LngeeX7W9SIWvfoJzbpQJqkZUSJXW8AuyD89Q6Zla+3aDptiLo5DsyG0iPdLO+RYHheCNUWaOo1Y9Dl0hFVQYnJJ0RAzqMxOzAol+jxdSJP8Tu7H79qTIJcXanjD4ov1MO1uuYfhBuy/a22yeVLP12mtey5gPhH9oOMsNZJxjEZ2Ly8uqKjkEA+rQInX1eaxi5umlsibf1MvNVFQBUMB0Ga/jNIs7mOkgGHVBdLlGZKrMbFMn6RGQDfDT6OW5/SCdLgi/vymOTgvW6r+xR3BXBx5iZzTzEoL0ed0Q67fpaWezk/aV2cTwdQELRBVioD6DGzJ0HVOgU4mOjAzJRnFrtq7qlezsKfCH6BLdbK7PrZ5vm61unCKArcOp8MDaxiFwBVhAwHR2cp1giz0fuZdmMqy9PInrKLfLWRfaflLyKG6dc65EiENmAG8JzpoqRQzHrz4L8tz1OXKmupkSZCzNQas4QBswv61QllHL5KSJ85/+jNjwTG2IakU7nt+RGk65sQSEro1C1tDzaBapaIdds3G92UiOlSVjB4dGCaykwP7phP3gUH6IlbManN4ij+WcnwYMlZZFdDI2oANX0Wycc7Na28tTGZBDDUTJkqjhq1nOFcoiKBuKhqyyr8LsXt8Ec5oKrpUjecMPjqO1ayfj60fFZ4zFewsyS0OtDtAlTxI7vzSLWPtMWSDGfUjhy36KKVZ7pdlqRp33GNn/5JAHFzLHIfA3CA3yp4pkWzC6Up87VJ9tpqyOJVdchxp6cJ8UPbE189pKspO35kHZlaQzI3Swdqa6mMBqoocI1ObDaXLFLiqDjj8oU0X+hiVtXlEd2WfDLfXHDKl0GIfCv9O09GqPoweLwKifDEOVPHxsCQn/qn2zCC7gCMy9yDruKjbyPcjvPvB0dxk+LdReCN1ZIXmZNffXTO7AgwyijUvjL2KTyzZUGsoik/TU6LBF/F0qRbkhyEfdW2rDhRjfhVAR06CwkSe7UeBy0pNQQJEH+bhSKt07DI7POYJLmaqlkEvhC0Vx3AMnU9Sb3+X9k/69ReDarWA3s0j6x8pIes0dqTnutvqgLtfdhO4+/vDgUQVyIVPWJM6sb3JyYlmYk4S7EwwINXvJ6elrB54qdh23dJjus= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230037)(7416011)(376011)(36860700010)(1800799021)(82310400023)(921017);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2024 20:06:04.0886 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bf1ae36e-3097-488e-9f0f-08dc8f08eadc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000066ED.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8453 CXL RAS errors are reported through AER interrupts using the AER status: correctbale internal errors (CIE) and AER uncorrectable internal errors (UIE).[1] But, the AER CIE/UIE are disabled by default preventing notification of CXL RAS errors.[2] Enable CXL PCIe port RAS notification by unmasking the ports' AER CIE and UIE errors. [1] CXL3.1 - 12.2.2 CXL Root Ports, Downstream Switch Ports, and Upstream Switch Ports [2] PCI6.0 - 7.8.4.3 Uncorrectable Error Mask Register (Offset 08h), 7.8.4.6 Correctable Error Mask Register (Offset 14h) Signed-off-by: Terry Bowman --- drivers/cxl/core/pci.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index e630eccb733d..73637d39df0a 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -861,6 +861,12 @@ void cxl_setup_parent_uport(struct device *host, struct cxl_port *port) struct device *uport_dev = port->uport_dev; cxl_port_map_regs(uport_dev, map, regs); + + if (dev_is_pci(uport_dev)) { + struct pci_dev *pdev = to_pci_dev(uport_dev); + + pci_aer_unmask_internal_errors(pdev); + } } EXPORT_SYMBOL_NS_GPL(cxl_setup_parent_uport, CXL); @@ -878,6 +884,12 @@ void cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport) if (dport->rch) cxl_disable_rch_root_ints(dport); + + if (dev_is_pci(dport_dev)) { + struct pci_dev *pdev = to_pci_dev(dport_dev); + + pci_aer_unmask_internal_errors(pdev); + } } EXPORT_SYMBOL_NS_GPL(cxl_setup_parent_dport, CXL);