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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1PEPF000066EC.mail.protection.outlook.com (10.167.249.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7677.15 via Frontend Transport; Mon, 17 Jun 2024 20:05:31 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 17 Jun 2024 15:05:29 -0500 From: Terry Bowman To: , , , , , , , , , , , , , , , Subject: [RFC PATCH 6/9] cxl/pci: Add trace logging for CXL PCIe port RAS errors Date: Mon, 17 Jun 2024 15:04:08 -0500 Message-ID: <20240617200411.1426554-7-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240617200411.1426554-1-terry.bowman@amd.com> References: <20240617200411.1426554-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000066EC:EE_|CH3PR12MB9316:EE_ X-MS-Office365-Filtering-Correlation-Id: dffeb003-480b-4610-1455-08dc8f08d750 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230037|36860700010|376011|7416011|82310400023|1800799021|921017; X-Microsoft-Antispam-Message-Info: r2UYczTk3XNFDdBNxSyg55ALPKe+LISxe74koy9CCUcX7KudDPQ4I+zYeGtixRL+wBMiJ8ms0VutyBd7VzeW2yRKIsMV8kUIc1NptN+Z9iCB0ccFjjFOrM44DjS48wRbBeI4ESKbVPoZ6n+KTzlwZbbot+6tA3Y9r2/SVmkVagJvdvqNpbmakp8dedEnxAwLycspppMQdVWEjswitfDXwVK/G4BXMEZ7RzwsoriZ+n4ulC/4p9lOr2swDqHDJmob8e//Lm2xZ5i2/oV/U9HaR7/GUps2yfyt+Yqgl2E3XsGaq07XJCsZb5X2o2PB5jTsZKXlc3WAoA6auA7Nvn0l8asSEiXWcbprppuEuGKR6JQrPa06mXrRTMl09kstVsKXCEubXR7qp2zBbDDYpXBN716r0CWExUqaeyorwOYU6GYVBUUR4jQ6T7jHTC7hnXAJJipej06v+T7OH8432P2lpB+EM7fc2IpUH5ue3DBgMRBg0DL0aHV1c/jAZe3MDMJicTJvzxrV0GyH8G2BHoSYRDIeiSENvUwSW+BpzxopjRS9S+XLZkYKibZrO3wg0O6syQfDX68bfsKarGHDP7tc84YxQgb7RHxF7zs9C7HkqSniLoMODdTvNUp2Qx+YH6USgmnIX2us4V6qLbBmfV/9uqFaXCFn3+fnRXX8IBofNjVzcgKMyPVL1W/xNi+MwiBzuMGavtA/5iml01jc5SLdwFXafJbAjueEHTUDd6hBnvNB7S6BsASUoEffhLa/n99lajTSzDSslX483OboGWiQ+6dxnMyb6JG+4C0McS8wLBH7xFOg2myrY2HrAk85KrRDlqjbagKuQFJsACTNq42GRAprVw8bm/4VfrRTLqaITahI1blevlcmCGPSEwc4Ih1Cpeoc1mVA5wuc1m3isEpY0dhMZUyOyDB8BWoKjvKfvpH3rqlRTxqgFz2XXddDsBsU/MsGTCdyY+k2s2jTVPHezySlO6r3oWWf2ft9Z8zsUps3m/wDps+ttL8U4emgWvetfINic59cyKluIDQ33kUEllC6ESlv4YbI69JL6fcp5QLj+gzZbP0SgcobDrCx5aCcJcuNl2h98gHbqfZdJHvxZUI7xL3PgQPR1tvdabqLXwj67hZ0ONfaBUYyeuAuHO9zKwx24sjn2JpE54/blD9CwKDFDIFSRlJIaSkg0UebiINwhfkYadit+aoKAEFlXKjQ1FUAzhu5VtrNZzXdQexeMKnfHYbz9lIgtpuDZVfjxUJPcVV29DfmpKcP/2cnZ5CIiOyxKlIHrSVb9p2tFDTxtLz5toV60/kGWe44q7VZDh6hQmwkmJrsSmJ7Mf0ECW8+YZPN2xlUH34oLU3RBoy+rftvXbgJTnwCBrre3SRCKur16xanKwU0WCjrPIQH0Z2f9sTZx7Zbvg2pRBmvDp/lhbqcm0S3r0QpGb5kmQa0wz4= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230037)(36860700010)(376011)(7416011)(82310400023)(1800799021)(921017);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2024 20:05:31.3065 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dffeb003-480b-4610-1455-08dc8f08d750 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000066EC.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9316 The cxl_pci driver uses kernel trace functions to log RAS errors for endpoints and RCH downstream ports. The same is needed for CXL root ports, CXL downstream switch ports, and CXL upstream switch ports. Add RAS correctable and RAS uncorrectable trace logging functions for CXL PCIE ports. Signed-off-by: Terry Bowman --- drivers/cxl/core/trace.h | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/drivers/cxl/core/trace.h b/drivers/cxl/core/trace.h index e5f13260fc52..5cfd9952d88a 100644 --- a/drivers/cxl/core/trace.h +++ b/drivers/cxl/core/trace.h @@ -48,6 +48,23 @@ { CXL_RAS_UC_IDE_RX_ERR, "IDE Rx Error" } \ ) +TRACE_EVENT(cxl_port_aer_uncorrectable_error, + TP_PROTO(struct device *dev, u32 status), + TP_ARGS(dev, status), + TP_STRUCT__entry( + __string(devname, dev_name(dev)) + __field(u32, status) + ), + TP_fast_assign( + __assign_str(devname, dev_name(dev)); + __entry->status = status; + ), + TP_printk("device=%s status='%s'", + __get_str(devname), + show_uc_errs(__entry->status) + ) +); + TRACE_EVENT(cxl_aer_uncorrectable_error, TP_PROTO(const struct cxl_memdev *cxlmd, u32 status, u32 fe, u32 *hl), TP_ARGS(cxlmd, status, fe, hl), @@ -96,6 +113,23 @@ TRACE_EVENT(cxl_aer_uncorrectable_error, { CXL_RAS_CE_PHYS_LAYER_ERR, "Received Error From Physical Layer" } \ ) +TRACE_EVENT(cxl_port_aer_correctable_error, + TP_PROTO(struct device *dev, u32 status), + TP_ARGS(dev, status), + TP_STRUCT__entry( + __string(devname, dev_name(dev)) + __field(u32, status) + ), + TP_fast_assign( + __assign_str(devname, dev_name(dev)); + __entry->status = status; + ), + TP_printk("device=%s status='%s'", + __get_str(devname), + show_ce_errs(__entry->status) + ) +); + TRACE_EVENT(cxl_aer_correctable_error, TP_PROTO(const struct cxl_memdev *cxlmd, u32 status), TP_ARGS(cxlmd, status),