diff mbox series

[v16,2/2] cxl/pci: Add sysfs attribute for CXL 1.1 device link status

Message ID 20240815005510.220835-4-kobayashi.da-06@fujitsu.com
State Superseded
Headers show
Series Export cxl1.1 device link status register value to pci device sysfs. | expand

Commit Message

Daisuke Kobayashi (Fujitsu) Aug. 15, 2024, 12:55 a.m. UTC 
Add sysfs attribute for CXL 1.1 device link status to the cxl pci device.

In CXL1.1, the link status of the device is included in the RCRB mapped to
the memory mapped register area. Critically, that arrangement makes the
link status and control registers invisible to existing PCI user tooling.

Export those registers via sysfs with the expectation that PCI user
tooling will alternatively look for these sysfs files when attempting to
access to these CXL 1.1 endpoints registers.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: "Kobayashi,Daisuke" <kobayashi.da-06@fujitsu.com>
---
 drivers/cxl/pci.c | 78 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 78 insertions(+)

Comments

Li, Ming4 Aug. 16, 2024, 6:56 a.m. UTC | #1 
On 8/15/2024 8:55 AM, Kobayashi,Daisuke wrote:
> Add sysfs attribute for CXL 1.1 device link status to the cxl pci device.
>
> In CXL1.1, the link status of the device is included in the RCRB mapped to
> the memory mapped register area. Critically, that arrangement makes the
> link status and control registers invisible to existing PCI user tooling.
>
> Export those registers via sysfs with the expectation that PCI user
> tooling will alternatively look for these sysfs files when attempting to
> access to these CXL 1.1 endpoints registers.
>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Signed-off-by: "Kobayashi,Daisuke" <kobayashi.da-06@fujitsu.com>
> ---
>  drivers/cxl/pci.c | 78 +++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 78 insertions(+)
>
> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> index 4eaf64d92541..4e51b6a0a97b 100644
> --- a/drivers/cxl/pci.c
> +++ b/drivers/cxl/pci.c
> @@ -792,6 +792,83 @@ static int cxl_event_config(struct pci_host_bridge *host_bridge,
>  	return 0;
>  }
>  
> +static ssize_t rcd_pcie_cap_emit(struct device *dev, u16 offset, char *buf, size_t width)
> +{
> +	struct cxl_dev_state *cxlds = dev_get_drvdata(dev);
> +	struct cxl_memdev *cxlmd = cxlds->cxlmd;
> +	struct device *root_dev;
> +	struct cxl_dport *dport;
> +	struct cxl_port *root __free(put_cxl_root) =
> +		cxl_mem_find_port(cxlmd, &dport);

It is not right to use put_cxl_root() to dereference a cxl_port->dev here. put_cxl_root() is used for a struct cxl_root rather than a struct cxl_port. I implemented a put_cxl_port() in the below patch which is under review.

https://lore.kernel.org/linux-cxl/20240813070552.3353530-1-ming4.li@intel.com/T/#m07695675435bf702311dfc40f64289b9623afa16


> +
> +	if (!root)
> +		return -ENXIO;
> +
> +	root_dev = root->uport_dev;
> +	if (!root_dev)
> +		return -ENXIO;
> +
> +	guard(device)(root_dev);
> +	if (!root_dev->driver)
> +		return -ENXIO;
> +
> +	switch (width) {
> +	case 2:
> +		return sysfs_emit(buf, "%#x\n",
> +				  readw(dport->regs.rcd_pcie_cap + offset));
> +	case 4:
> +		return sysfs_emit(buf, "%#x\n",
> +				  readl(dport->regs.rcd_pcie_cap + offset));
> +	default:
> +		return -EINVAL;
> +	}
> +}
> +
> +static ssize_t rcd_link_cap_show(struct device *dev,
> +				 struct device_attribute *attr, char *buf)
> +{
> +	return rcd_pcie_cap_emit(dev, PCI_EXP_LNKCAP, buf, sizeof(u32));
> +}
> +static DEVICE_ATTR_RO(rcd_link_cap);
> +
> +static ssize_t rcd_link_ctrl_show(struct device *dev,
> +				  struct device_attribute *attr, char *buf)
> +{
> +	return rcd_pcie_cap_emit(dev, PCI_EXP_LNKCTL, buf, sizeof(u16));
> +}
> +static DEVICE_ATTR_RO(rcd_link_ctrl);
> +
> +static ssize_t rcd_link_status_show(struct device *dev,
> +				    struct device_attribute *attr, char *buf)
> +{
> +	return rcd_pcie_cap_emit(dev, PCI_EXP_LNKSTA, buf, sizeof(u16));
> +}
> +static DEVICE_ATTR_RO(rcd_link_status);
> +
> +static struct attribute *cxl_rcd_attrs[] = {
> +	&dev_attr_rcd_link_cap.attr,
> +	&dev_attr_rcd_link_ctrl.attr,
> +	&dev_attr_rcd_link_status.attr,
> +	NULL
> +};
> +
> +static umode_t cxl_rcd_visible(struct kobject *kobj, struct attribute *a, int n)
> +{
> +	struct device *dev = kobj_to_dev(kobj);
> +	struct pci_dev *pdev = to_pci_dev(dev);
> +
> +	if (is_cxl_restricted(pdev))
> +		return a->mode;
> +
> +	return 0;
> +}
> +
> +static struct attribute_group cxl_rcd_group = {
> +	.attrs = cxl_rcd_attrs,
> +	.is_visible = cxl_rcd_visible,
> +};
> +__ATTRIBUTE_GROUPS(cxl_rcd);
> +
>  static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
>  {
>  	struct pci_host_bridge *host_bridge = pci_find_host_bridge(pdev->bus);
> @@ -975,6 +1052,7 @@ static struct pci_driver cxl_pci_driver = {
>  	.id_table		= cxl_mem_pci_tbl,
>  	.probe			= cxl_pci_probe,
>  	.err_handler		= &cxl_error_handlers,
> +	.dev_groups		= cxl_rcd_groups,
>  	.driver	= {
>  		.probe_type	= PROBE_PREFER_ASYNCHRONOUS,
>  	},
Daisuke Kobayashi (Fujitsu) Aug. 19, 2024, 5:52 a.m. UTC | #2 
Li,Ming wrote:
> On 8/15/2024 8:55 AM, Kobayashi,Daisuke wrote:
> > Add sysfs attribute for CXL 1.1 device link status to the cxl pci device.
> >
> > In CXL1.1, the link status of the device is included in the RCRB mapped to
> > the memory mapped register area. Critically, that arrangement makes the
> > link status and control registers invisible to existing PCI user tooling.
> >
> > Export those registers via sysfs with the expectation that PCI user
> > tooling will alternatively look for these sysfs files when attempting to
> > access to these CXL 1.1 endpoints registers.
> >
> > Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > Signed-off-by: "Kobayashi,Daisuke" <kobayashi.da-06@fujitsu.com>
> > ---
> >  drivers/cxl/pci.c | 78
> +++++++++++++++++++++++++++++++++++++++++++++++
> >  1 file changed, 78 insertions(+)
> >
> > diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> > index 4eaf64d92541..4e51b6a0a97b 100644
> > --- a/drivers/cxl/pci.c
> > +++ b/drivers/cxl/pci.c
> > @@ -792,6 +792,83 @@ static int cxl_event_config(struct pci_host_bridge
> *host_bridge,
> >  	return 0;
> >  }
> >
> > +static ssize_t rcd_pcie_cap_emit(struct device *dev, u16 offset, char *buf,
> size_t width)
> > +{
> > +	struct cxl_dev_state *cxlds = dev_get_drvdata(dev);
> > +	struct cxl_memdev *cxlmd = cxlds->cxlmd;
> > +	struct device *root_dev;
> > +	struct cxl_dport *dport;
> > +	struct cxl_port *root __free(put_cxl_root) =
> > +		cxl_mem_find_port(cxlmd, &dport);
> 
> It is not right to use put_cxl_root() to dereference a cxl_port->dev here.
> put_cxl_root() is used for a struct cxl_root rather than a struct cxl_port. I
> implemented a put_cxl_port() in the below patch which is under review.
> 
> https://lore.kernel.org/linux-cxl/20240813070552.3353530-1-ming4.li@intel.c
> om/T/#m07695675435bf702311dfc40f64289b9623afa16
> 
> 
Thank you for your comment.
It seems I misunderstood Dan's review comment. It appears that using the function is the correct approach.

Dan, could you please confirm that your review comment is suggesting the use of this function which is under review?


> > +
> > +	if (!root)
> > +		return -ENXIO;
> > +
> > +	root_dev = root->uport_dev;
> > +	if (!root_dev)
> > +		return -ENXIO;
> > +
> > +	guard(device)(root_dev);
> > +	if (!root_dev->driver)
> > +		return -ENXIO;
> > +
> > +	switch (width) {
> > +	case 2:
> > +		return sysfs_emit(buf, "%#x\n",
> > +				  readw(dport->regs.rcd_pcie_cap +
> offset));
> > +	case 4:
> > +		return sysfs_emit(buf, "%#x\n",
> > +				  readl(dport->regs.rcd_pcie_cap + offset));
> > +	default:
> > +		return -EINVAL;
> > +	}
> > +}
> > +
> > +static ssize_t rcd_link_cap_show(struct device *dev,
> > +				 struct device_attribute *attr, char *buf)
> > +{
> > +	return rcd_pcie_cap_emit(dev, PCI_EXP_LNKCAP, buf, sizeof(u32));
> > +}
> > +static DEVICE_ATTR_RO(rcd_link_cap);
> > +
> > +static ssize_t rcd_link_ctrl_show(struct device *dev,
> > +				  struct device_attribute *attr, char *buf)
> > +{
> > +	return rcd_pcie_cap_emit(dev, PCI_EXP_LNKCTL, buf, sizeof(u16));
> > +}
> > +static DEVICE_ATTR_RO(rcd_link_ctrl);
> > +
> > +static ssize_t rcd_link_status_show(struct device *dev,
> > +				    struct device_attribute *attr, char *buf)
> > +{
> > +	return rcd_pcie_cap_emit(dev, PCI_EXP_LNKSTA, buf, sizeof(u16));
> > +}
> > +static DEVICE_ATTR_RO(rcd_link_status);
> > +
> > +static struct attribute *cxl_rcd_attrs[] = {
> > +	&dev_attr_rcd_link_cap.attr,
> > +	&dev_attr_rcd_link_ctrl.attr,
> > +	&dev_attr_rcd_link_status.attr,
> > +	NULL
> > +};
> > +
> > +static umode_t cxl_rcd_visible(struct kobject *kobj, struct attribute *a, int
> n)
> > +{
> > +	struct device *dev = kobj_to_dev(kobj);
> > +	struct pci_dev *pdev = to_pci_dev(dev);
> > +
> > +	if (is_cxl_restricted(pdev))
> > +		return a->mode;
> > +
> > +	return 0;
> > +}
> > +
> > +static struct attribute_group cxl_rcd_group = {
> > +	.attrs = cxl_rcd_attrs,
> > +	.is_visible = cxl_rcd_visible,
> > +};
> > +__ATTRIBUTE_GROUPS(cxl_rcd);
> > +
> >  static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id
> *id)
> >  {
> >  	struct pci_host_bridge *host_bridge =
> pci_find_host_bridge(pdev->bus);
> > @@ -975,6 +1052,7 @@ static struct pci_driver cxl_pci_driver = {
> >  	.id_table		= cxl_mem_pci_tbl,
> >  	.probe			= cxl_pci_probe,
> >  	.err_handler		= &cxl_error_handlers,
> > +	.dev_groups		= cxl_rcd_groups,
> >  	.driver	= {
> >  		.probe_type	= PROBE_PREFER_ASYNCHRONOUS,
> >  	},
>
diff mbox series

Patch

diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index 4eaf64d92541..4e51b6a0a97b 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -792,6 +792,83 @@  static int cxl_event_config(struct pci_host_bridge *host_bridge,
 	return 0;
 }
 
+static ssize_t rcd_pcie_cap_emit(struct device *dev, u16 offset, char *buf, size_t width)
+{
+	struct cxl_dev_state *cxlds = dev_get_drvdata(dev);
+	struct cxl_memdev *cxlmd = cxlds->cxlmd;
+	struct device *root_dev;
+	struct cxl_dport *dport;
+	struct cxl_port *root __free(put_cxl_root) =
+		cxl_mem_find_port(cxlmd, &dport);
+
+	if (!root)
+		return -ENXIO;
+
+	root_dev = root->uport_dev;
+	if (!root_dev)
+		return -ENXIO;
+
+	guard(device)(root_dev);
+	if (!root_dev->driver)
+		return -ENXIO;
+
+	switch (width) {
+	case 2:
+		return sysfs_emit(buf, "%#x\n",
+				  readw(dport->regs.rcd_pcie_cap + offset));
+	case 4:
+		return sysfs_emit(buf, "%#x\n",
+				  readl(dport->regs.rcd_pcie_cap + offset));
+	default:
+		return -EINVAL;
+	}
+}
+
+static ssize_t rcd_link_cap_show(struct device *dev,
+				 struct device_attribute *attr, char *buf)
+{
+	return rcd_pcie_cap_emit(dev, PCI_EXP_LNKCAP, buf, sizeof(u32));
+}
+static DEVICE_ATTR_RO(rcd_link_cap);
+
+static ssize_t rcd_link_ctrl_show(struct device *dev,
+				  struct device_attribute *attr, char *buf)
+{
+	return rcd_pcie_cap_emit(dev, PCI_EXP_LNKCTL, buf, sizeof(u16));
+}
+static DEVICE_ATTR_RO(rcd_link_ctrl);
+
+static ssize_t rcd_link_status_show(struct device *dev,
+				    struct device_attribute *attr, char *buf)
+{
+	return rcd_pcie_cap_emit(dev, PCI_EXP_LNKSTA, buf, sizeof(u16));
+}
+static DEVICE_ATTR_RO(rcd_link_status);
+
+static struct attribute *cxl_rcd_attrs[] = {
+	&dev_attr_rcd_link_cap.attr,
+	&dev_attr_rcd_link_ctrl.attr,
+	&dev_attr_rcd_link_status.attr,
+	NULL
+};
+
+static umode_t cxl_rcd_visible(struct kobject *kobj, struct attribute *a, int n)
+{
+	struct device *dev = kobj_to_dev(kobj);
+	struct pci_dev *pdev = to_pci_dev(dev);
+
+	if (is_cxl_restricted(pdev))
+		return a->mode;
+
+	return 0;
+}
+
+static struct attribute_group cxl_rcd_group = {
+	.attrs = cxl_rcd_attrs,
+	.is_visible = cxl_rcd_visible,
+};
+__ATTRIBUTE_GROUPS(cxl_rcd);
+
 static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 {
 	struct pci_host_bridge *host_bridge = pci_find_host_bridge(pdev->bus);
@@ -975,6 +1052,7 @@  static struct pci_driver cxl_pci_driver = {
 	.id_table		= cxl_mem_pci_tbl,
 	.probe			= cxl_pci_probe,
 	.err_handler		= &cxl_error_handlers,
+	.dev_groups		= cxl_rcd_groups,
 	.driver	= {
 		.probe_type	= PROBE_PREFER_ASYNCHRONOUS,
 	},