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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN3PEPF0000B078.mail.protection.outlook.com (10.167.243.123) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8048.13 via Frontend Transport; Tue, 8 Oct 2024 22:17:15 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 8 Oct 2024 17:17:14 -0500 From: Terry Bowman To: , , , , , , , , , , , , , , , , , Subject: [PATCH 01/15] cxl/aer/pci: Add CXL PCIe port error handler callbacks in AER service driver Date: Tue, 8 Oct 2024 17:16:43 -0500 Message-ID: <20241008221657.1130181-2-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241008221657.1130181-1-terry.bowman@amd.com> References: <20241008221657.1130181-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B078:EE_|SJ2PR12MB8159:EE_ X-MS-Office365-Filtering-Correlation-Id: dbbf03eb-a5d0-41d5-0394-08dce7e6f6fe X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|1800799024|36860700013|7416014|921020; X-Microsoft-Antispam-Message-Info: 68BUTrfqrAkzFAo0Da87kN0FeUuI1sjuDq1G/qKHk/O+q//MFWxJ1ZQjpKvJTS9wzo/hvtaBZji1GaOBOnWY7iThQTSDYPiQ0O+yQAsaKBzc7qGXnXi0DCgjoyXBNOyrT2/i+Ni4zG5pHrxUdhHRzU+YT3HALW648olO/YAIfUjw7OsbFGfQ9TSfdBCKq8nqSXLvcyZ7iQiuuISVMCxCDzmKUH77dQeUjtvM661+GlJEXXQyF5cCDw8czcNs9iF1wHBplb60iqq4kiCpaMiDV1Z0ck14RCC7Z4Y2JzfJqR8rXWimlAZnGLPhVN7/o9SFMEHRLX5w7/1EH8Vuv+O3ai/71nm4XXjOhnY91yc3ToRXAMz6qykHb17yJMq9GLFYkerwatMjEf/2b79Oog0Y3z4dtk1PytuSh6luKAQqU65zZVT6DGM66yJqt3OsRc71Jg2y5R1zoqwLaWl5yu+ugwsSmEdl3AN3bV3KinTM7/2VdKb0sVsMTChTbCAoOgyt5v7fcPUZWprXCqQRfiX7iskX/HTZnfp9SFbiBBtionmHoIfJmgX2N/3bMjQ18MjRocY3cfsHORXZMyoFtqLTOQXzoExbSaqk4bMngYYHyZpayFzxowjL6pBDYWuM0S1Y+NZ0hw5lO73Tpa1Q1/RV7Plvyu+LK1Y+IbyubswlqSufAIUOinM1Ppj9C9zqBz1/JNsZ77a2YRqhayZNTLl5Nwcd33L/yAjyL5sZRDTukYmmg/nxRI/MzM5fw9SJeU92DCYpM+byBkf2qr6JtY+kR1Ll+Gr+/1Rju1FpbBAy0uC6IK8lc/ZTDPJwr6EXnuIEPMBU3PtL/57CGaTg96IiuJ2H73NwdWcmbkJhUlJTjA3JfXUEJVrZOvv9eV1kcGraVKfqZek4FKe6Y+CnYfQS1Feah10WT+zKokI1XVvtFJrPFam/SXCYZRYjex5n8C23Afpc5hbvD2pSLnODGLoNiiZogkaXz1VTwNAt+Pqk97GYhkCOgF/HorcYDnyAjkc0kG2XfSW3RHZgJvyFlOOX8M6D/sW7aC9QvnYfxlOadN/V/bX/geINB1WABZO5V8psZPrNI4qy/QCgyn6Gm26r0+H0BkXSVo4JmVLhjQwBWmY8KnUzNHL88wWRHNwMxz2w8b+U7lFY7zBShIMjzs8/NV4qQlQXz7mmv0lnRwhxfdubWiCWeKm59ccE/jWI4kruKjjiM8ZhrUk9P9v81lBSCKONSWXjX7verDB7oWvOkEQuRYMKhzsnXpf46hXpEBsOQ8PUCXgNstOFUEvW8Lml1eUYR7pIM02IaBUu+GOoA1O2grd+CUlyVmwSnGXWoT8L89UgSgt75yHCg5skIGp4Zzw+hZ18z4bxAQ1r+JkgOzTRwJGMf+vgipnypjqQ6TJW X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(82310400026)(1800799024)(36860700013)(7416014)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2024 22:17:15.1323 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dbbf03eb-a5d0-41d5-0394-08dce7e6f6fe X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B078.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8159 CXL protocol errors are reported to the OS through PCIe correctable and uncorrectable internal errors. However, since CXL PCIe port devices are currently bound to the portdrv driver, there is no mechanism to notify the CXL driver, which is necessary for proper logging and handling. To address this, introduce CXL PCIe port error callbacks along with register/unregister and accessor functions. The callbacks will be invoked by the AER driver in the case protocol errors are reported by a CXL port device. The AER driver callbacks will be used in future patches implementing CXL PCIe port error handling. Signed-off-by: Terry Bowman --- drivers/pci/pcie/aer.c | 22 ++++++++++++++++++++++ include/linux/aer.h | 14 ++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 13b8586924ea..a9792b9576b4 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -50,6 +50,8 @@ struct aer_rpc { DECLARE_KFIFO(aer_fifo, struct aer_err_source, AER_ERROR_SOURCES_MAX); }; +static struct cxl_port_err_hndlrs cxl_port_hndlrs; + /* AER stats for the device */ struct aer_stats { @@ -1078,6 +1080,26 @@ static inline void cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info *info) { } #endif +void register_cxl_port_hndlrs(struct cxl_port_err_hndlrs *_cxl_port_hndlrs) +{ + cxl_port_hndlrs.error_detected = _cxl_port_hndlrs->error_detected; + cxl_port_hndlrs.cor_error_detected = _cxl_port_hndlrs->cor_error_detected; +} +EXPORT_SYMBOL_NS_GPL(register_cxl_port_hndlrs, CXL); + +void unregister_cxl_port_hndlrs(void) +{ + cxl_port_hndlrs.error_detected = NULL; + cxl_port_hndlrs.cor_error_detected = NULL; +} +EXPORT_SYMBOL_NS_GPL(unregister_cxl_port_hndlrs, CXL); + +struct cxl_port_err_hndlrs *find_cxl_port_hndlrs(void) +{ + return &cxl_port_hndlrs; +} +EXPORT_SYMBOL_NS_GPL(find_cxl_port_hndlrs, CXL); + /** * pci_aer_handle_error - handle logging error into an event log * @dev: pointer to pci_dev data structure of error source device diff --git a/include/linux/aer.h b/include/linux/aer.h index 4b97f38f3fcf..67fd04c5ae2b 100644 --- a/include/linux/aer.h +++ b/include/linux/aer.h @@ -10,6 +10,7 @@ #include #include +#include #define AER_NONFATAL 0 #define AER_FATAL 1 @@ -55,5 +56,18 @@ void pci_print_aer(struct pci_dev *dev, int aer_severity, int cper_severity_to_aer(int cper_severity); void aer_recover_queue(int domain, unsigned int bus, unsigned int devfn, int severity, struct aer_capability_regs *aer_regs); + +struct cxl_port_err_hndlrs { + + /* CXL uncorrectable error detected on this device */ + pci_ers_result_t (*error_detected)(struct pci_dev *dev, + pci_channel_state_t error); + + /* CXL corrected error detected on this device */ + void (*cor_error_detected)(struct pci_dev *dev); +}; +void register_cxl_port_hndlrs(struct cxl_port_err_hndlrs *_cxl_port_hndlrs); +void unregister_cxl_port_hndlrs(void); +struct cxl_port_err_hndlrs *find_cxl_port_hndlrs(void); #endif //_AER_H_