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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C Received: from SATLEXMB03.amd.com (165.204.84.17) by SN1PEPF00026368.mail.protection.outlook.com (10.167.241.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8069.17 via Frontend Transport; Thu, 17 Oct 2024 16:53:19 +0000 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 17 Oct 2024 11:53:19 -0500 Received: from xcbalucerop41x.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39 via Frontend Transport; Thu, 17 Oct 2024 11:53:17 -0500 From: To: , , , , , , , , CC: Alejandro Lucero Subject: [PATCH v4 05/26] cxl: move pci generic code Date: Thu, 17 Oct 2024 17:52:04 +0100 Message-ID: <20241017165225.21206-6-alejandro.lucero-palau@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241017165225.21206-1-alejandro.lucero-palau@amd.com> References: <20241017165225.21206-1-alejandro.lucero-palau@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Received-SPF: None (SATLEXMB03.amd.com: alejandro.lucero-palau@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF00026368:EE_|CH3PR12MB8877:EE_ X-MS-Office365-Filtering-Correlation-Id: d21cd61c-ad96-4e08-ac88-08dceecc3462 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|376014|1800799024; X-Microsoft-Antispam-Message-Info: PZzZUTOHEXxvNQ0wY8VMuJHVeOjzYCa6BeRRQTl0zOqJOu9bKppxEGxmQEAHz6xZ5gvwOzlb2CkAkyJiw4fp/NMe1jneXJtH6w4mUVo8qVfutTDkLxttqNgLSTz6t2m5XHcl3ULhbFd10OFfc6ChcV84OW9zRz53PYhPGq/HEEXGrsxNC41CZwm0lA3sGeebXYRE6dlQ+X9ej267eESOdKz30bnEiGsOHZQDl+N21jBFdZLPtrvwEphE7f/ziXZyk21xF4LeP8CiYRTX8HRQ1/MgRqOKVMlOxrBIrncDhz/ZG65VX02+pcsmsXdtq+7cIB4PPBNPXxvvq/0MmSPsmiHn331Lf83Lzj2+AI7zHEebLtRrcwWGM60hS8nv17zyIw7/zOQzzvvUytoNm39JBSiK7+HgOhZblKM8YPQKgz6zYZuWhjCgAqH1+ylmyBF25jyOpC6XPGtllU9aolyhrE0+d+lqgMheIsqZJxAkiVABJBj22jURhBe7+8Ev1ncBxcxk4cTJNwjvnlH6KdUoME1issyzWt9r2h6tV6wYZ0PGFBOQS/WJ4PEhSU093v33uCdJaIFGGTj2w3zQlRXYtZvHRWbwqFFjywKxyfZx1r6dFQB2CSJ0DIWDbx+I9/T+QGBNflpHznZVMTodo+mJdSnxwywLdV3MFzCdODkiOkYXLx5pU67CJQn84/R8QS9GE9jdGY3MevKccilk7XF38A5kCOcu8zlWX4y6OP15bPJHTVshRm52E+jV8Xo+BCDBAT0H5bI5DrT01LIII1TV4psRpekABKUFMQw/IuhQjsZG4LfN+6/KfxStkq75ctkN9MIXz29Q6W33dyTYo6Q5Cazisu/t/QzI4hGRcRODYGJXlMtr3sFY6pDWtFLCmpNbTEP37251DXw8IpjHZSLa42AN/C8uD36IP+fwhrXwyNO/AbdEhzlB3agrroh8xxfm1JWFWEGIXe0lg2Cc8sOsUhHy0NdE+USsXco7VEtZBPTUEnGR3ixJYM6k0LnHWjSkyVdO5spdTMBKUIK+yySJJnD8zEGIt6b0F9uIOpG+7tgaPuO66dkTXXGIR1+C8ZcUG7HyH8X/lbZmU+byYe9OxcQuxPInik+73uu82UBTx38GH1f5gUs/FxM/X4EZuX2IgbBlhIk1m4g5ay6cj8RQj8bBlY3wlRYvywwQfmWryIMN5Zgy5J+Fo+uUtlS3aIMuLvhReagDUEonrrczvAc8QkKgocYlNHghcJZ5/S812NtN0TF5cZIud6xCx/3+b9DW4MF7k8vqCB92I2LJcKaWUJE0IxNsPKn4IZsq1Pk5SFyb2QFTjgvT2qTs4743I677k975foA0jPhchpJ/Fr7gV/bJ8TVSXIpm8E12fWZv2eA33UvUi1bYA++oNXIdmpXINL0V5uvJ344Ou+PzQuxUFQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Oct 2024 16:53:19.8607 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d21cd61c-ad96-4e08-ac88-08dceecc3462 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00026368.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8877 From: Alejandro Lucero Inside cxl/core/pci.c there are helpers for CXL PCIe initialization meanwhile cxl/pci.c implements the functionality for a Type3 device initialization. Move helper functions from cxl/pci.c to cxl/pci/pci.c in order to be exported and shared with CXL Type2 device initialization. Signed-off-by: Alejandro Lucero --- drivers/cxl/core/pci.c | 62 ++++++++++++++++++++++++++++++++++++++++++ drivers/cxl/cxlpci.h | 3 ++ drivers/cxl/pci.c | 61 ----------------------------------------- 3 files changed, 65 insertions(+), 61 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index fa2a5e216dc3..99acc258722d 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -1079,6 +1079,68 @@ bool cxl_endpoint_decoder_reset_detected(struct cxl_port *port) } EXPORT_SYMBOL_NS_GPL(cxl_endpoint_decoder_reset_detected, CXL); +/* + * Assume that any RCIEP that emits the CXL memory expander class code + * is an RCD + */ +bool is_cxl_restricted(struct pci_dev *pdev) +{ + return pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END; +} +EXPORT_SYMBOL_NS_GPL(is_cxl_restricted, CXL); + +static int cxl_rcrb_get_comp_regs(struct pci_dev *pdev, + struct cxl_register_map *map) +{ + struct cxl_port *port; + struct cxl_dport *dport; + resource_size_t component_reg_phys; + + *map = (struct cxl_register_map) { + .host = &pdev->dev, + .resource = CXL_RESOURCE_NONE, + }; + + port = cxl_pci_find_port(pdev, &dport); + if (!port) + return -EPROBE_DEFER; + + component_reg_phys = cxl_rcd_component_reg_phys(&pdev->dev, dport); + + put_device(&port->dev); + + if (component_reg_phys == CXL_RESOURCE_NONE) + return -ENXIO; + + map->resource = component_reg_phys; + map->reg_type = CXL_REGLOC_RBI_COMPONENT; + map->max_size = CXL_COMPONENT_REG_BLOCK_SIZE; + + return 0; +} + +int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, + struct cxl_register_map *map, unsigned long *caps) +{ + int rc; + + rc = cxl_find_regblock(pdev, type, map); + + /* + * If the Register Locator DVSEC does not exist, check if it + * is an RCH and try to extract the Component Registers from + * an RCRB. + */ + if (rc && type == CXL_REGLOC_RBI_COMPONENT && is_cxl_restricted(pdev)) + rc = cxl_rcrb_get_comp_regs(pdev, map); + + if (rc) + return rc; + + return cxl_setup_regs(map, caps); +} +EXPORT_SYMBOL_NS_GPL(cxl_pci_setup_regs, CXL); + bool cxl_pci_check_caps(struct cxl_dev_state *cxlds, unsigned long *expected_caps, unsigned long *current_caps) { diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h index eb59019fe5f3..985cca3c3350 100644 --- a/drivers/cxl/cxlpci.h +++ b/drivers/cxl/cxlpci.h @@ -113,4 +113,7 @@ void read_cdat_data(struct cxl_port *port); void cxl_cor_error_detected(struct pci_dev *pdev); pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, pci_channel_state_t state); +bool is_cxl_restricted(struct pci_dev *pdev); +int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, + struct cxl_register_map *map, unsigned long *caps); #endif /* __CXL_PCI_H__ */ diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 89c8ac1a61fd..e9333211e18f 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -463,67 +463,6 @@ static int cxl_pci_setup_mailbox(struct cxl_memdev_state *mds, bool irq_avail) return 0; } -/* - * Assume that any RCIEP that emits the CXL memory expander class code - * is an RCD - */ -static bool is_cxl_restricted(struct pci_dev *pdev) -{ - return pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END; -} - -static int cxl_rcrb_get_comp_regs(struct pci_dev *pdev, - struct cxl_register_map *map) -{ - struct cxl_port *port; - struct cxl_dport *dport; - resource_size_t component_reg_phys; - - *map = (struct cxl_register_map) { - .host = &pdev->dev, - .resource = CXL_RESOURCE_NONE, - }; - - port = cxl_pci_find_port(pdev, &dport); - if (!port) - return -EPROBE_DEFER; - - component_reg_phys = cxl_rcd_component_reg_phys(&pdev->dev, dport); - - put_device(&port->dev); - - if (component_reg_phys == CXL_RESOURCE_NONE) - return -ENXIO; - - map->resource = component_reg_phys; - map->reg_type = CXL_REGLOC_RBI_COMPONENT; - map->max_size = CXL_COMPONENT_REG_BLOCK_SIZE; - - return 0; -} - -static int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, - struct cxl_register_map *map, - unsigned long *caps) -{ - int rc; - - rc = cxl_find_regblock(pdev, type, map); - - /* - * If the Register Locator DVSEC does not exist, check if it - * is an RCH and try to extract the Component Registers from - * an RCRB. - */ - if (rc && type == CXL_REGLOC_RBI_COMPONENT && is_cxl_restricted(pdev)) - rc = cxl_rcrb_get_comp_regs(pdev, map); - - if (rc) - return rc; - - return cxl_setup_regs(map, caps); -} - static int cxl_pci_ras_unmask(struct pci_dev *pdev) { struct cxl_dev_state *cxlds = pci_get_drvdata(pdev);