| Message ID | 20241025114555.1363-7-shiju.jose@huawei.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Update Event Records to CXL spec rev 3.1 | expand |
On Fri, 25 Oct 2024 12:45:55 +0100 <shiju.jose@huawei.com> wrote: > From: Shiju Jose <shiju.jose@huawei.com> > > Update test code for General Media, DRAM, Memory Module Event > Records to CXL spec rev 3.1. > > Signed-off-by: Shiju Jose <shiju.jose@huawei.com> I ran the test and it looked sensible. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Tested-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Side note, cxl_test fails on ARM due to attempting to hotplug memory outside of the PA range the system supports. Problem for another day when I'll either fix it post a proper bug report. Jonathan > --- > tools/testing/cxl/test/mem.c | 23 ++++++++++++++++++++--- > 1 file changed, 20 insertions(+), 3 deletions(-) > > diff --git a/tools/testing/cxl/test/mem.c b/tools/testing/cxl/test/mem.c > index ad5c4c18c5c6..614783eb3f84 100644 > --- a/tools/testing/cxl/test/mem.c > +++ b/tools/testing/cxl/test/mem.c > @@ -401,6 +401,10 @@ struct cxl_test_gen_media gen_media = { > .channel = 1, > .rank = 30, > }, > + .component_id = { 0x3, 0x74, 0xc5, 0x8, 0x9a, 0x1a, 0xb, 0xfc, 0xd2, 0x7e, 0x2f, 0x31, 0x9b, 0x3c, 0x81, 0x4d }, > + .cme_threshold_ev_flags = 3, > + .cme_count = { 33, 0, 0 }, > + .sub_type = 0x2, > }, > }; > > @@ -429,6 +433,11 @@ struct cxl_test_dram dram = { > .bank_group = 5, > .bank = 2, > .column = {0xDE, 0xAD}, > + .component_id = { 0x1, 0x74, 0xc5, 0x8, 0x9a, 0x1a, 0xb, 0xfc, 0xd2, 0x7e, 0x2f, 0x31, 0x9b, 0x3c, 0x81, 0x4d }, > + .sub_channel = 8, > + .cme_threshold_ev_flags = 2, > + .cvme_count = { 14, 0, 0 }, > + .sub_type = 0x5, > }, > }; > > @@ -456,7 +465,10 @@ struct cxl_test_mem_module mem_module = { > .dirty_shutdown_cnt = { 0xde, 0xad, 0xbe, 0xef }, > .cor_vol_err_cnt = { 0xde, 0xad, 0xbe, 0xef }, > .cor_per_err_cnt = { 0xde, 0xad, 0xbe, 0xef }, > - } > + }, > + /* .validity_flags = <set below> */ > + .component_id = { 0x2, 0x74, 0xc5, 0x8, 0x9a, 0x1a, 0xb, 0xfc, 0xd2, 0x7e, 0x2f, 0x31, 0x9b, 0x3c, 0x81, 0x4d }, > + .event_sub_type = 0x3, > }, > }; > > @@ -478,13 +490,18 @@ static int mock_set_timestamp(struct cxl_dev_state *cxlds, > > static void cxl_mock_add_event_logs(struct mock_event_store *mes) > { > - put_unaligned_le16(CXL_GMER_VALID_CHANNEL | CXL_GMER_VALID_RANK, > + put_unaligned_le16(CXL_GMER_VALID_CHANNEL | CXL_GMER_VALID_RANK | > + CXL_GMER_VALID_COMPONENT | CXL_GMER_VALID_COMPONENT_ID_FORMAT, > &gen_media.rec.media_hdr.validity_flags); > > put_unaligned_le16(CXL_DER_VALID_CHANNEL | CXL_DER_VALID_BANK_GROUP | > - CXL_DER_VALID_BANK | CXL_DER_VALID_COLUMN, > + CXL_DER_VALID_BANK | CXL_DER_VALID_COLUMN | CXL_DER_VALID_SUB_CHANNEL | > + CXL_DER_VALID_COMPONENT | CXL_DER_VALID_COMPONENT_ID_FORMAT, > &dram.rec.media_hdr.validity_flags); > > + put_unaligned_le16(CXL_MMER_VALID_COMPONENT | CXL_MMER_VALID_COMPONENT_ID_FORMAT, > + &mem_module.rec.validity_flags); > + > mes_add_event(mes, CXL_EVENT_TYPE_INFO, &maint_needed); > mes_add_event(mes, CXL_EVENT_TYPE_INFO, > (struct cxl_event_record_raw *)&gen_media);
diff --git a/tools/testing/cxl/test/mem.c b/tools/testing/cxl/test/mem.c index ad5c4c18c5c6..614783eb3f84 100644 --- a/tools/testing/cxl/test/mem.c +++ b/tools/testing/cxl/test/mem.c @@ -401,6 +401,10 @@ struct cxl_test_gen_media gen_media = { .channel = 1, .rank = 30, }, + .component_id = { 0x3, 0x74, 0xc5, 0x8, 0x9a, 0x1a, 0xb, 0xfc, 0xd2, 0x7e, 0x2f, 0x31, 0x9b, 0x3c, 0x81, 0x4d }, + .cme_threshold_ev_flags = 3, + .cme_count = { 33, 0, 0 }, + .sub_type = 0x2, }, }; @@ -429,6 +433,11 @@ struct cxl_test_dram dram = { .bank_group = 5, .bank = 2, .column = {0xDE, 0xAD}, + .component_id = { 0x1, 0x74, 0xc5, 0x8, 0x9a, 0x1a, 0xb, 0xfc, 0xd2, 0x7e, 0x2f, 0x31, 0x9b, 0x3c, 0x81, 0x4d }, + .sub_channel = 8, + .cme_threshold_ev_flags = 2, + .cvme_count = { 14, 0, 0 }, + .sub_type = 0x5, }, }; @@ -456,7 +465,10 @@ struct cxl_test_mem_module mem_module = { .dirty_shutdown_cnt = { 0xde, 0xad, 0xbe, 0xef }, .cor_vol_err_cnt = { 0xde, 0xad, 0xbe, 0xef }, .cor_per_err_cnt = { 0xde, 0xad, 0xbe, 0xef }, - } + }, + /* .validity_flags = <set below> */ + .component_id = { 0x2, 0x74, 0xc5, 0x8, 0x9a, 0x1a, 0xb, 0xfc, 0xd2, 0x7e, 0x2f, 0x31, 0x9b, 0x3c, 0x81, 0x4d }, + .event_sub_type = 0x3, }, }; @@ -478,13 +490,18 @@ static int mock_set_timestamp(struct cxl_dev_state *cxlds, static void cxl_mock_add_event_logs(struct mock_event_store *mes) { - put_unaligned_le16(CXL_GMER_VALID_CHANNEL | CXL_GMER_VALID_RANK, + put_unaligned_le16(CXL_GMER_VALID_CHANNEL | CXL_GMER_VALID_RANK | + CXL_GMER_VALID_COMPONENT | CXL_GMER_VALID_COMPONENT_ID_FORMAT, &gen_media.rec.media_hdr.validity_flags); put_unaligned_le16(CXL_DER_VALID_CHANNEL | CXL_DER_VALID_BANK_GROUP | - CXL_DER_VALID_BANK | CXL_DER_VALID_COLUMN, + CXL_DER_VALID_BANK | CXL_DER_VALID_COLUMN | CXL_DER_VALID_SUB_CHANNEL | + CXL_DER_VALID_COMPONENT | CXL_DER_VALID_COMPONENT_ID_FORMAT, &dram.rec.media_hdr.validity_flags); + put_unaligned_le16(CXL_MMER_VALID_COMPONENT | CXL_MMER_VALID_COMPONENT_ID_FORMAT, + &mem_module.rec.validity_flags); + mes_add_event(mes, CXL_EVENT_TYPE_INFO, &maint_needed); mes_add_event(mes, CXL_EVENT_TYPE_INFO, (struct cxl_event_record_raw *)&gen_media);