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Mon, 18 Nov 2024 10:44:52 -0600 From: To: , , , , , , , , CC: Alejandro Lucero Subject: [PATCH v5 07/27] sfc: use cxl api for regs setup and checking Date: Mon, 18 Nov 2024 16:44:14 +0000 Message-ID: <20241118164434.7551-8-alejandro.lucero-palau@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241118164434.7551-1-alejandro.lucero-palau@amd.com> References: <20241118164434.7551-1-alejandro.lucero-palau@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A0FB:EE_|PH0PR12MB7840:EE_ X-MS-Office365-Filtering-Correlation-Id: db6165fa-e798-456e-c4c2-08dd07f057e4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: lR20ZHID1EPSqYUXmEmIX1QeTBNq6YQsHl8xy1jgA6ff1QZm0No6R24R5gVFe0b2EW29cDEKyuKwHIG33fOWQVJ31lyzdNXewxnFbbSQV+ExKh/3NB5LyO+keAZ3Yl+EV2nMl3liEIAuLZK5XGTy/k4faW3Yd9iheib8r6oUWOVKxsmypJbtfT5svifBOxR7qm3OuhuZjpa288JpXfXEoJRasOQFAToccvgYJncg7puPoOHRmdgWkrI20bpC6uBg9J4moq5XvHqmqrIrXnRYlonvMr+qF+4/LLpsTV7TL4l0HHzopCB/Q6Sv8ZZIPAK4LnKBhJpobYDfi8naQGzrnJf7SMzjDnTDrbAGUzmMUFhD4yeQ0hn1dAszviJc9B36nJfSLEUHYsWhZHkQZqevFQ3V+N6JHATMBi/yH/DgOPQFQ8tCqbgdeSp+9Ix5JLTP2eRGC2NWVJZUmxmeyL56VS665+sQZJ8+nkJQNZRvQxIRR+BPhovw+L0Qv+WX/xC+A3x4+MK470bKaIssVgFE9T55zBM4PuYstQnr7I5tMcM4ehSSIOXEOVeTJJND5ii7B8ma4ABKUfA2KoVvdzyAiYh7VXAX1y/jfljudTrRtg3FzNoQBlmlyhVdF0wPiQs4XxAftsqkFYf1oHX96HgtVtIFkF0VhSa2Tm9XBDHGNAML1dOusAufBU6WIrM4Qcq/Ln/sAqeFYF4hZVNFF+YY3py61plQISRORM0O8Ivuj/QR7kQ9CHWP88W2FYgark5pluRSJMalMJuw91I4xjwTxeDyOz2MTC26B5vRN8WllGMN1UugfUo8tZHqqDl0kbRN9Ep8v3oRtgiXNCrUkuYdICWxzLf+G1L6UiXpobrbF00I4h/h70lzVNiEpXikkQMXLBtKyOLRgv/Gp/uDDE5S/BW1O2hVdr8+BpoImcq+y3Gb6IsyEa3nIhKQSXNHsXBt3ppGk4EiZ9y8Uid4deD9oSsQCpapOEINNvzVMYO8MyfJcoVaiAtq07jlc1Ww7AviCHKtQZkkNttAzZPn0WZuZbc1g+dVQSaO6Uebe8qo+ksZmgHqyZ6L/Laiqn0rV/+/ltU1E8H/N1fp2xtDuYwHARlEK25JyHh30rscPfEXfVkGDVGZ3ZfX8iyxdX4RIEoxSy2C3SBdzAdXhLdPCptO3hgdmCaoaWEP0rXZjoAJ5JMlkD7fZtFVh789GIey4NaZC6x02WZsIh7bSYNxN198W9ouK0Ks6BEhG/4fk95c/RNx3svMG0jaNjYOO26/wbO6mTdTpXtG7QAtdmXp9KGphtngWN9o26UUdAy+c3MCMx6ufDx6yukGX32g09JvNVpDeV/aBq9IW+HWTJf67xq0eJztE2/eF6EEifuTZ0TpN3/zVWYZVy03Z+a+uXBRxERhazmojnqzGvZdRrkWi5YUPw== X-Forefront-Antispam-Report: CIP:165.204.84.12;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:atlvpn-bp.amd.com;CAT:NONE;SFS:(13230040)(376014)(1800799024)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Nov 2024 16:45:00.4009 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: db6165fa-e798-456e-c4c2-08dd07f057e4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.12];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A0FB.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB7840 From: Alejandro Lucero Use cxl code for registers discovery and mapping. Validate capabilities found based on those registers against expected capabilities. Signed-off-by: Alejandro Lucero --- drivers/net/ethernet/sfc/efx_cxl.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/net/ethernet/sfc/efx_cxl.c b/drivers/net/ethernet/sfc/efx_cxl.c index 99f396028639..d6afd1b5499f 100644 --- a/drivers/net/ethernet/sfc/efx_cxl.c +++ b/drivers/net/ethernet/sfc/efx_cxl.c @@ -21,6 +21,8 @@ int efx_cxl_init(struct efx_probe_data *probe_data) { struct efx_nic *efx = &probe_data->efx; + DECLARE_BITMAP(expected, CXL_MAX_CAPS); + DECLARE_BITMAP(found, CXL_MAX_CAPS); struct pci_dev *pci_dev; struct efx_cxl *cxl; struct resource res; @@ -65,6 +67,23 @@ int efx_cxl_init(struct efx_probe_data *probe_data) goto err2; } + rc = cxl_pci_accel_setup_regs(pci_dev, cxl->cxlds); + if (rc) { + pci_err(pci_dev, "CXL accel setup regs failed"); + goto err2; + } + + bitmap_clear(expected, 0, CXL_MAX_CAPS); + bitmap_set(expected, CXL_DEV_CAP_HDM, 1); + bitmap_set(expected, CXL_DEV_CAP_RAS, 1); + + if (!cxl_pci_check_caps(cxl->cxlds, expected, found, false)) { + pci_err(pci_dev, + "CXL device capabilities found(%08lx) not as expected(%08lx)", + *found, *expected); + goto err2; + } + probe_data->cxl = cxl; return 0;