diff mbox series

[3/3] cxl/test: Simulate an x86 Low Memory Hole for tests

Message ID 20241122155226.2068287-4-fabio.m.de.francesco@linux.intel.com
State New
Headers show
Series cxl/core: Enable Region creation on x86 with Low Mem Hole | expand

Commit Message

Fabio M. De Francesco Nov. 22, 2024, 3:51 p.m. UTC 
Simulate an x86 Low Memory Hole for the CXL tests by changing
mock_cfmws[0] range size to 768MB and CXL Endpoint Decoder HPA range size
to 1GB and have get_cfmws_range_start() return two different addresses
which depend on whether the passed device is real or mock.

Cc: Alison Schofield <alison.schofield@intel.com>
Cc: Dan Williams <dan.j.williams@intel.com>
Cc: Ira Weiny <ira.weiny@intel.com>
Signed-off-by: Fabio M. De Francesco <fabio.m.de.francesco@linux.intel.com>
---
 drivers/cxl/core/lmh.c       | 21 +++++++++++++--------
 drivers/cxl/cxl.h            |  7 +++++++
 tools/testing/cxl/Kbuild     |  1 +
 tools/testing/cxl/test/cxl.c |  4 ++--
 4 files changed, 23 insertions(+), 10 deletions(-)

Comments

Ira Weiny Nov. 22, 2024, 5:26 p.m. UTC | #1 
Fabio M. De Francesco wrote:
> Simulate an x86 Low Memory Hole for the CXL tests by changing
> mock_cfmws[0] range size to 768MB and CXL Endpoint Decoder HPA range size
> to 1GB and have get_cfmws_range_start() return two different addresses
> which depend on whether the passed device is real or mock.
> 
> Cc: Alison Schofield <alison.schofield@intel.com>
> Cc: Dan Williams <dan.j.williams@intel.com>
> Cc: Ira Weiny <ira.weiny@intel.com>
> Signed-off-by: Fabio M. De Francesco <fabio.m.de.francesco@linux.intel.com>

Nice!

Reviewed-by: Ira Weiny <ira.weiny@intel.com>
diff mbox series

Patch

diff --git a/drivers/cxl/core/lmh.c b/drivers/cxl/core/lmh.c
index da76b2a534ec..350008324bdc 100644
--- a/drivers/cxl/core/lmh.c
+++ b/drivers/cxl/core/lmh.c
@@ -1,10 +1,15 @@ 
 // SPDX-License-Identifier: GPL-2.0-only
 
 #include <linux/range.h>
+#include <linux/pci.h>
 #include "cxl.h"
 
-/* In x86 with memory hole, misaligned CFMWS range starts at 0x0 */
-#define MISALIGNED_CFMWS_RANGE_BASE 0x0
+u64 get_cfmws_range_start(struct device *dev)
+{
+	if (dev_is_pci(dev))
+		return MISALIGNED_CFMWS_RANGE_START;
+	return MISALIGNED_MOCK_CFMWS_RANGE_START;
+}
 
 /*
  * Match CXL Root and Endpoint Decoders by comparing SPA and HPA ranges.
@@ -17,6 +22,7 @@ 
 bool arch_match_spa(struct cxl_root_decoder *cxlrd,
 		    struct cxl_endpoint_decoder *cxled)
 {
+	u64 cfmws_range_start = get_cfmws_range_start(&cxled->cxld.dev);
 	struct range *r1, *r2;
 	int niw;
 
@@ -24,9 +30,8 @@  bool arch_match_spa(struct cxl_root_decoder *cxlrd,
 	r2 = &cxled->cxld.hpa_range;
 	niw = cxled->cxld.interleave_ways;
 
-	if (r1->start == MISALIGNED_CFMWS_RANGE_BASE &&
-	    r1->start == r2->start && r1->end < r2->end &&
-	    IS_ALIGNED(range_len(r2), niw * SZ_256M))
+	if (r1->start == cfmws_range_start && r1->start == r2->start &&
+	    r1->end < r2->end && IS_ALIGNED(range_len(r2), niw * SZ_256M))
 		return true;
 	return false;
 }
@@ -35,13 +40,13 @@  bool arch_match_spa(struct cxl_root_decoder *cxlrd,
 bool arch_match_region(struct cxl_region_params *p,
 		       struct cxl_decoder *cxld)
 {
+	u64 cfmws_range_start = get_cfmws_range_start(&cxld->dev);
 	struct range *r = &cxld->hpa_range;
 	struct resource *res = p->res;
 	int niw = cxld->interleave_ways;
 
-	if (res->start == MISALIGNED_CFMWS_RANGE_BASE &&
-	    res->start == r->start && res->end < r->end &&
-	    IS_ALIGNED(range_len(r), niw * SZ_256M))
+	if (res->start == cfmws_range_start && res->start == r->start &&
+	    res->end < r->end && IS_ALIGNED(range_len(r), niw * SZ_256M))
 		return true;
 	return false;
 }
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index a5ad4499381e..51dc80f8e50c 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -903,12 +903,19 @@  void cxl_coordinates_combine(struct access_coordinate *out,
 bool cxl_endpoint_decoder_reset_detected(struct cxl_port *port);
 
 #ifdef CONFIG_CXL_ARCH_LOW_MEMORY_HOLE
+
+/* Range start address of misaligned CFMWS in x86 with LMH */
+#define MISALIGNED_CFMWS_RANGE_START 0x0
+/* Range start address of mock misaligned CFMWS for tests */
+#define MISALIGNED_MOCK_CFMWS_RANGE_START 0xf010000000
+
 bool arch_match_spa(struct cxl_root_decoder *cxlrd,
 		    struct cxl_endpoint_decoder *cxled);
 bool arch_match_region(struct cxl_region_params *p,
 		       struct cxl_decoder *cxld);
 void arch_trim_hpa_by_spa(struct resource *res,
 			  struct cxl_root_decoder *cxlrd);
+u64 get_cfmws_range_start(struct device *dev);
 #else
 bool arch_match_spa(struct cxl_root_decoder *cxlrd,
 		    struct cxl_endpoint_decoder *cxled)
diff --git a/tools/testing/cxl/Kbuild b/tools/testing/cxl/Kbuild
index b1256fee3567..fe9c4480f758 100644
--- a/tools/testing/cxl/Kbuild
+++ b/tools/testing/cxl/Kbuild
@@ -62,6 +62,7 @@  cxl_core-y += $(CXL_CORE_SRC)/hdm.o
 cxl_core-y += $(CXL_CORE_SRC)/pmu.o
 cxl_core-y += $(CXL_CORE_SRC)/cdat.o
 cxl_core-$(CONFIG_TRACING) += $(CXL_CORE_SRC)/trace.o
+cxl_core-$(CONFIG_CXL_ARCH_LOW_MEMORY_HOLE) += $(CXL_CORE_SRC)/lmh.o
 cxl_core-$(CONFIG_CXL_REGION) += $(CXL_CORE_SRC)/region.o
 cxl_core-y += config_check.o
 cxl_core-y += cxl_core_test.o
diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c
index 050725afa45d..b61c3d78fed3 100644
--- a/tools/testing/cxl/test/cxl.c
+++ b/tools/testing/cxl/test/cxl.c
@@ -212,7 +212,7 @@  static struct {
 			.restrictions = ACPI_CEDT_CFMWS_RESTRICT_TYPE3 |
 					ACPI_CEDT_CFMWS_RESTRICT_VOLATILE,
 			.qtg_id = FAKE_QTG_ID,
-			.window_size = SZ_256M * 4UL,
+			.window_size = SZ_256M * 3UL,
 		},
 		.target = { 0 },
 	},
@@ -744,7 +744,7 @@  static void mock_init_hdm_decoder(struct cxl_decoder *cxld)
 	struct cxl_endpoint_decoder *cxled;
 	struct cxl_switch_decoder *cxlsd;
 	struct cxl_port *port, *iter;
-	const int size = SZ_512M;
+	const int size = SZ_1G;
 	struct cxl_memdev *cxlmd;
 	struct cxl_dport *dport;
 	struct device *dev;