| Message ID | 20241230214445.27602-7-alejandro.lucero-palau@amd.com |
|---|---|
| State | New |
| Headers | show |
| Series | cxl: add type2 device basic support | expand |
On Mon, 30 Dec 2024 21:44:24 +0000 <alejandro.lucero-palau@amd.com> wrote: > From: Alejandro Lucero <alucerop@amd.com> > > Create a new function for a type2 device initialising > cxl_dev_state struct regarding cxl regs setup and mapping. > > Signed-off-by: Alejandro Lucero <alucerop@amd.com> > Reviewed-by: Dave Jiang <dave.jiang@intel.com> > Reviewed-by: Fan Ni <fan.ni@samsung.com> Hi Alejandro I think there was one additional change you were going to make based on v8 feedback. See inline. With that add Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > --- > drivers/cxl/core/pci.c | 51 ++++++++++++++++++++++++++++++++++++++++++ > include/cxl/cxl.h | 2 ++ > 2 files changed, 53 insertions(+) > > diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c > index 5821d582c520..493ab33fe771 100644 > --- a/drivers/cxl/core/pci.c > +++ b/drivers/cxl/core/pci.c > @@ -1107,6 +1107,57 @@ int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, > } > EXPORT_SYMBOL_NS_GPL(cxl_pci_setup_regs, "CXL"); > > +static int cxl_pci_setup_memdev_regs(struct pci_dev *pdev, > + struct cxl_dev_state *cxlds) > +{ > + struct cxl_register_map map; > + int rc; > + > + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map, > + cxlds->capabilities); > + /* > + * This call can return -ENODEV if regs not found. This is not an error > + * for Type2 since these regs are not mandatory. If they do exist then > + * mapping them should not fail. If they should exist, it is with driver > + * calling cxl_pci_check_caps where the problem should be found. > + */ > + if (rc == -ENODEV) > + return 0; > + > + if (rc) > + return rc; > + > + return cxl_map_device_regs(&map, &cxlds->regs.device_regs); > +} > + > +int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_dev_state *cxlds) > +{ > + int rc; > + > + rc = cxl_pci_setup_memdev_regs(pdev, cxlds); > + if (rc) > + return rc; > + > + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, > + &cxlds->reg_map, cxlds->capabilities); > + if (rc) { > + dev_warn(&pdev->dev, "No component registers (%d)\n", rc); > + return rc; > + } > + > + if (!test_bit(CXL_CM_CAP_CAP_ID_RAS, cxlds->capabilities)) > + return rc; return 0; will make it clear what intent is here. > + > + rc = cxl_map_component_regs(&cxlds->reg_map, > + &cxlds->regs.component, > + BIT(CXL_CM_CAP_CAP_ID_RAS)); > + if (rc) > + dev_dbg(&pdev->dev, "Failed to map RAS capability.\n"); > + > + return rc; > +} > +EXPORT_SYMBOL_NS_GPL(cxl_pci_accel_setup_regs, "CXL");
On 1/2/25 14:53, Jonathan Cameron wrote: > On Mon, 30 Dec 2024 21:44:24 +0000 > <alejandro.lucero-palau@amd.com> wrote: > >> From: Alejandro Lucero <alucerop@amd.com> >> >> Create a new function for a type2 device initialising >> cxl_dev_state struct regarding cxl regs setup and mapping. >> >> Signed-off-by: Alejandro Lucero <alucerop@amd.com> >> Reviewed-by: Dave Jiang <dave.jiang@intel.com> >> Reviewed-by: Fan Ni <fan.ni@samsung.com> > Hi Alejandro > > I think there was one additional change you were going to make based > on v8 feedback. Oh, I just commented there agreeing with that (and the other one) but forgot this one. I'll do it in v10. Thanks > See inline. With that add > > Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > >> --- >> drivers/cxl/core/pci.c | 51 ++++++++++++++++++++++++++++++++++++++++++ >> include/cxl/cxl.h | 2 ++ >> 2 files changed, 53 insertions(+) >> >> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c >> index 5821d582c520..493ab33fe771 100644 >> --- a/drivers/cxl/core/pci.c >> +++ b/drivers/cxl/core/pci.c >> @@ -1107,6 +1107,57 @@ int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, >> } >> EXPORT_SYMBOL_NS_GPL(cxl_pci_setup_regs, "CXL"); >> >> +static int cxl_pci_setup_memdev_regs(struct pci_dev *pdev, >> + struct cxl_dev_state *cxlds) >> +{ >> + struct cxl_register_map map; >> + int rc; >> + >> + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map, >> + cxlds->capabilities); >> + /* >> + * This call can return -ENODEV if regs not found. This is not an error >> + * for Type2 since these regs are not mandatory. If they do exist then >> + * mapping them should not fail. If they should exist, it is with driver >> + * calling cxl_pci_check_caps where the problem should be found. >> + */ >> + if (rc == -ENODEV) >> + return 0; >> + >> + if (rc) >> + return rc; >> + >> + return cxl_map_device_regs(&map, &cxlds->regs.device_regs); >> +} >> + >> +int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_dev_state *cxlds) >> +{ >> + int rc; >> + >> + rc = cxl_pci_setup_memdev_regs(pdev, cxlds); >> + if (rc) >> + return rc; >> + >> + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, >> + &cxlds->reg_map, cxlds->capabilities); >> + if (rc) { >> + dev_warn(&pdev->dev, "No component registers (%d)\n", rc); >> + return rc; >> + } >> + >> + if (!test_bit(CXL_CM_CAP_CAP_ID_RAS, cxlds->capabilities)) >> + return rc; > return 0; > > will make it clear what intent is here. > >> + >> + rc = cxl_map_component_regs(&cxlds->reg_map, >> + &cxlds->regs.component, >> + BIT(CXL_CM_CAP_CAP_ID_RAS)); >> + if (rc) >> + dev_dbg(&pdev->dev, "Failed to map RAS capability.\n"); >> + >> + return rc; >> +} >> +EXPORT_SYMBOL_NS_GPL(cxl_pci_accel_setup_regs, "CXL");
alejandro.lucero-palau@ wrote: > From: Alejandro Lucero <alucerop@amd.com> > > Create a new function for a type2 device initialising > cxl_dev_state struct regarding cxl regs setup and mapping. > > Signed-off-by: Alejandro Lucero <alucerop@amd.com> > Reviewed-by: Dave Jiang <dave.jiang@intel.com> > Reviewed-by: Fan Ni <fan.ni@samsung.com> > --- > drivers/cxl/core/pci.c | 51 ++++++++++++++++++++++++++++++++++++++++++ > include/cxl/cxl.h | 2 ++ > 2 files changed, 53 insertions(+) > > diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c > index 5821d582c520..493ab33fe771 100644 > --- a/drivers/cxl/core/pci.c > +++ b/drivers/cxl/core/pci.c > @@ -1107,6 +1107,57 @@ int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, > } > EXPORT_SYMBOL_NS_GPL(cxl_pci_setup_regs, "CXL"); > > +static int cxl_pci_setup_memdev_regs(struct pci_dev *pdev, > + struct cxl_dev_state *cxlds) > +{ > + struct cxl_register_map map; > + int rc; > + > + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map, > + cxlds->capabilities); > + /* > + * This call can return -ENODEV if regs not found. This is not an error > + * for Type2 since these regs are not mandatory. If they do exist then > + * mapping them should not fail. If they should exist, it is with driver > + * calling cxl_pci_check_caps where the problem should be found. > + */ There is no common definition of type-2 so the core should not try to assume it knows, or be told what is mandatory. Just export the raw helpers and leave it to the caller to make these decisions. > + if (rc == -ENODEV) > + return 0; > + > + if (rc) > + return rc; > + > + return cxl_map_device_regs(&map, &cxlds->regs.device_regs); > +} > + > +int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_dev_state *cxlds) > +{ > + int rc; > + > + rc = cxl_pci_setup_memdev_regs(pdev, cxlds); > + if (rc) > + return rc; > + > + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, > + &cxlds->reg_map, cxlds->capabilities); > + if (rc) { > + dev_warn(&pdev->dev, "No component registers (%d)\n", rc); > + return rc; > + } > + > + if (!test_bit(CXL_CM_CAP_CAP_ID_RAS, cxlds->capabilities)) > + return rc; > + > + rc = cxl_map_component_regs(&cxlds->reg_map, > + &cxlds->regs.component, > + BIT(CXL_CM_CAP_CAP_ID_RAS)); > + if (rc) > + dev_dbg(&pdev->dev, "Failed to map RAS capability.\n"); > + > + return rc; > +} > +EXPORT_SYMBOL_NS_GPL(cxl_pci_accel_setup_regs, "CXL"); Only after we have multiple instances of CXL accelerator drivers that start copying the same init code should a helper be created that wraps that duplication. Otherwise move this probing and error determination out to SFC for now.
On 1/18/25 01:51, Dan Williams wrote: > alejandro.lucero-palau@ wrote: >> From: Alejandro Lucero <alucerop@amd.com> >> >> Create a new function for a type2 device initialising >> cxl_dev_state struct regarding cxl regs setup and mapping. >> >> Signed-off-by: Alejandro Lucero <alucerop@amd.com> >> Reviewed-by: Dave Jiang <dave.jiang@intel.com> >> Reviewed-by: Fan Ni <fan.ni@samsung.com> >> --- >> drivers/cxl/core/pci.c | 51 ++++++++++++++++++++++++++++++++++++++++++ >> include/cxl/cxl.h | 2 ++ >> 2 files changed, 53 insertions(+) >> >> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c >> index 5821d582c520..493ab33fe771 100644 >> --- a/drivers/cxl/core/pci.c >> +++ b/drivers/cxl/core/pci.c >> @@ -1107,6 +1107,57 @@ int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, >> } >> EXPORT_SYMBOL_NS_GPL(cxl_pci_setup_regs, "CXL"); >> >> +static int cxl_pci_setup_memdev_regs(struct pci_dev *pdev, >> + struct cxl_dev_state *cxlds) >> +{ >> + struct cxl_register_map map; >> + int rc; >> + >> + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map, >> + cxlds->capabilities); >> + /* >> + * This call can return -ENODEV if regs not found. This is not an error >> + * for Type2 since these regs are not mandatory. If they do exist then >> + * mapping them should not fail. If they should exist, it is with driver >> + * calling cxl_pci_check_caps where the problem should be found. >> + */ > There is no common definition of type-2 so the core should not try to > assume it knows, or be told what is mandatory. Just export the raw > helpers and leave it to the caller to make these decisions. The code does not know, but it knows it does not know, therefore handles this new situation not needed before Type2 support in the generic code for the pci driver and Type3. This is added to the API for accel drivers following the design restrictions I have commented earlier in another patch. Your suggestion seems to go against that decision what was implicitly taken after the first versions and which had no complains until now. More about this same issue below. >> + if (rc == -ENODEV) >> + return 0; >> + >> + if (rc) >> + return rc; >> + >> + return cxl_map_device_regs(&map, &cxlds->regs.device_regs); >> +} >> + >> +int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_dev_state *cxlds) >> +{ >> + int rc; >> + >> + rc = cxl_pci_setup_memdev_regs(pdev, cxlds); >> + if (rc) >> + return rc; >> + >> + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, >> + &cxlds->reg_map, cxlds->capabilities); >> + if (rc) { >> + dev_warn(&pdev->dev, "No component registers (%d)\n", rc); >> + return rc; >> + } >> + >> + if (!test_bit(CXL_CM_CAP_CAP_ID_RAS, cxlds->capabilities)) >> + return rc; >> + >> + rc = cxl_map_component_regs(&cxlds->reg_map, >> + &cxlds->regs.component, >> + BIT(CXL_CM_CAP_CAP_ID_RAS)); >> + if (rc) >> + dev_dbg(&pdev->dev, "Failed to map RAS capability.\n"); >> + >> + return rc; >> +} >> +EXPORT_SYMBOL_NS_GPL(cxl_pci_accel_setup_regs, "CXL"); > Only after we have multiple instances of CXL accelerator drivers that > start copying the same init code should a helper be created that wraps > that duplication. Otherwise move this probing and error determination > out to SFC for now. I do not think moving this to the accel driver makes sense at this point, but I think it is worth to try to share this as much as possible with the current pci driver for Type3.
Alejandro Lucero Palau wrote: > > On 1/18/25 01:51, Dan Williams wrote: > > alejandro.lucero-palau@ wrote: > >> From: Alejandro Lucero <alucerop@amd.com> > >> > >> Create a new function for a type2 device initialising > >> cxl_dev_state struct regarding cxl regs setup and mapping. > >> > >> Signed-off-by: Alejandro Lucero <alucerop@amd.com> > >> Reviewed-by: Dave Jiang <dave.jiang@intel.com> > >> Reviewed-by: Fan Ni <fan.ni@samsung.com> > >> --- > >> drivers/cxl/core/pci.c | 51 ++++++++++++++++++++++++++++++++++++++++++ > >> include/cxl/cxl.h | 2 ++ > >> 2 files changed, 53 insertions(+) > >> > >> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c > >> index 5821d582c520..493ab33fe771 100644 > >> --- a/drivers/cxl/core/pci.c > >> +++ b/drivers/cxl/core/pci.c > >> @@ -1107,6 +1107,57 @@ int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, > >> } > >> EXPORT_SYMBOL_NS_GPL(cxl_pci_setup_regs, "CXL"); > >> > >> +static int cxl_pci_setup_memdev_regs(struct pci_dev *pdev, > >> + struct cxl_dev_state *cxlds) > >> +{ > >> + struct cxl_register_map map; > >> + int rc; > >> + > >> + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map, > >> + cxlds->capabilities); > >> + /* > >> + * This call can return -ENODEV if regs not found. This is not an error > >> + * for Type2 since these regs are not mandatory. If they do exist then > >> + * mapping them should not fail. If they should exist, it is with driver > >> + * calling cxl_pci_check_caps where the problem should be found. > >> + */ > > There is no common definition of type-2 so the core should not try to > > assume it knows, or be told what is mandatory. Just export the raw > > helpers and leave it to the caller to make these decisions. > > > The code does not know, but it knows it does not know, therefore handles > this new situation not needed before Type2 support in the generic code > for the pci driver and Type3. > > This is added to the API for accel drivers following the design > restrictions I have commented earlier in another patch. Your suggestion > seems to go against that decision what was implicitly taken after the > first versions and which had no complains until now. Apologies for that, I had not looked at the implications of that general decision until now, but the result is going in the wrong direction from what it is doing to the core. > >> + return 0; > >> + > >> + if (rc) > >> + return rc; > >> + > >> + return cxl_map_device_regs(&map, &cxlds->regs.device_regs); > >> +} > >> + > >> +int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_dev_state *cxlds) > >> +{ > >> + int rc; > >> + > >> + rc = cxl_pci_setup_memdev_regs(pdev, cxlds); > >> + if (rc) > >> + return rc; > >> + > >> + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, > >> + &cxlds->reg_map, cxlds->capabilities); > >> + if (rc) { > >> + dev_warn(&pdev->dev, "No component registers (%d)\n", rc); > >> + return rc; > >> + } > >> + > >> + if (!test_bit(CXL_CM_CAP_CAP_ID_RAS, cxlds->capabilities)) > >> + return rc; This is injecting logic in a bitmap and a new CXL core exported ABI just to avoid the driver optionally skipping RAS register enumeration. The core should not care how and whether endpoint drivers (accel or cxl_pci) consume register blocks, just arrange for their enumeration and let the leaf driver logic take it from there.
On 1/21/25 22:51, Dan Williams wrote: > Alejandro Lucero Palau wrote: >> On 1/18/25 01:51, Dan Williams wrote: >>> alejandro.lucero-palau@ wrote: >>>> From: Alejandro Lucero <alucerop@amd.com> >>>> >>>> Create a new function for a type2 device initialising >>>> cxl_dev_state struct regarding cxl regs setup and mapping. >>>> >>>> Signed-off-by: Alejandro Lucero <alucerop@amd.com> >>>> Reviewed-by: Dave Jiang <dave.jiang@intel.com> >>>> Reviewed-by: Fan Ni <fan.ni@samsung.com> >>>> --- >>>> drivers/cxl/core/pci.c | 51 ++++++++++++++++++++++++++++++++++++++++++ >>>> include/cxl/cxl.h | 2 ++ >>>> 2 files changed, 53 insertions(+) >>>> >>>> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c >>>> index 5821d582c520..493ab33fe771 100644 >>>> --- a/drivers/cxl/core/pci.c >>>> +++ b/drivers/cxl/core/pci.c >>>> @@ -1107,6 +1107,57 @@ int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, >>>> } >>>> EXPORT_SYMBOL_NS_GPL(cxl_pci_setup_regs, "CXL"); >>>> >>>> +static int cxl_pci_setup_memdev_regs(struct pci_dev *pdev, >>>> + struct cxl_dev_state *cxlds) >>>> +{ >>>> + struct cxl_register_map map; >>>> + int rc; >>>> + >>>> + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map, >>>> + cxlds->capabilities); >>>> + /* >>>> + * This call can return -ENODEV if regs not found. This is not an error >>>> + * for Type2 since these regs are not mandatory. If they do exist then >>>> + * mapping them should not fail. If they should exist, it is with driver >>>> + * calling cxl_pci_check_caps where the problem should be found. >>>> + */ >>> There is no common definition of type-2 so the core should not try to >>> assume it knows, or be told what is mandatory. Just export the raw >>> helpers and leave it to the caller to make these decisions. >> >> The code does not know, but it knows it does not know, therefore handles >> this new situation not needed before Type2 support in the generic code >> for the pci driver and Type3. >> >> This is added to the API for accel drivers following the design >> restrictions I have commented earlier in another patch. Your suggestion >> seems to go against that decision what was implicitly taken after the >> first versions and which had no complains until now. > Apologies for that, I had not looked at the implications of that general > decision until now, but the result is going in the wrong direction from > what it is doing to the core. After yesterday's meeting listening to Jonathan and you discussing last reviews, what I thought was mainly related to this patchset, I was not sure I had to address this concern, but it is clear now. I'm a bit disappointed this requiring new design after so many cycles and about something I thought it was set and consensus existed. Anyway, I'll work on that, not sure yet what I should change and what should stay, because the main reason for the current design of an accel driver API does not exist anymore. I need time for figuring out the work to do, so DCD should take priority now for trying to merge it with 6.14. > >>>> + return 0; >>>> + >>>> + if (rc) >>>> + return rc; >>>> + >>>> + return cxl_map_device_regs(&map, &cxlds->regs.device_regs); >>>> +} >>>> + >>>> +int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_dev_state *cxlds) >>>> +{ >>>> + int rc; >>>> + >>>> + rc = cxl_pci_setup_memdev_regs(pdev, cxlds); >>>> + if (rc) >>>> + return rc; >>>> + >>>> + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, >>>> + &cxlds->reg_map, cxlds->capabilities); >>>> + if (rc) { >>>> + dev_warn(&pdev->dev, "No component registers (%d)\n", rc); >>>> + return rc; >>>> + } >>>> + >>>> + if (!test_bit(CXL_CM_CAP_CAP_ID_RAS, cxlds->capabilities)) >>>> + return rc; > This is injecting logic in a bitmap and a new CXL core exported ABI just > to avoid the driver optionally skipping RAS register enumeration. > > The core should not care how and whether endpoint drivers (accel or > cxl_pci) consume register blocks, just arrange for their enumeration and > let the leaf driver logic take it from there.
Alejandro Lucero Palau wrote: [..] > > Apologies for that, I had not looked at the implications of that general > > decision until now, but the result is going in the wrong direction from > > what it is doing to the core. > > After yesterday's meeting listening to Jonathan and you discussing last > reviews, what I thought was mainly related to this patchset, I was not > sure I had to address this concern, but it is clear now. > > I'm a bit disappointed this requiring new design after so many cycles > and about something I thought it was set and consensus existed. That is valid frustration, and there was indeed long silence on this patchset from me until recently. > Anyway, I'll work on that, not sure yet what I should change and what > should stay, because the main reason for the current design of an accel > driver API does not exist anymore. Yes, I think this was the main disconnect. The CXL core is a library, the expander use case is supported by a class code, the accelerator use case is an a la carte subset plus some disjoint bits. The library should be use case agnostic. That means that accelerator specific exports should be avoided especially when they are just wrapping other existing library exports. Push the use case specific concerns to the leaf drivers. Another way to put it is that new exports from drivers/cxl/ and core data structure touches will receive higher scrutiny, because that is new maintenance burden on the core. > I need time for figuring out the work to do, so DCD should take priority > now for trying to merge it with 6.14. This is all a bit too late unfortunately and I do not want to pressure Dave to explain to Linus why patches are still flowing into the CXL tree during the merge window. Lets get this wrapped up and in cxl.next early in the v6.15 cycle.
diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 5821d582c520..493ab33fe771 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -1107,6 +1107,57 @@ int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, } EXPORT_SYMBOL_NS_GPL(cxl_pci_setup_regs, "CXL"); +static int cxl_pci_setup_memdev_regs(struct pci_dev *pdev, + struct cxl_dev_state *cxlds) +{ + struct cxl_register_map map; + int rc; + + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map, + cxlds->capabilities); + /* + * This call can return -ENODEV if regs not found. This is not an error + * for Type2 since these regs are not mandatory. If they do exist then + * mapping them should not fail. If they should exist, it is with driver + * calling cxl_pci_check_caps where the problem should be found. + */ + if (rc == -ENODEV) + return 0; + + if (rc) + return rc; + + return cxl_map_device_regs(&map, &cxlds->regs.device_regs); +} + +int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_dev_state *cxlds) +{ + int rc; + + rc = cxl_pci_setup_memdev_regs(pdev, cxlds); + if (rc) + return rc; + + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, + &cxlds->reg_map, cxlds->capabilities); + if (rc) { + dev_warn(&pdev->dev, "No component registers (%d)\n", rc); + return rc; + } + + if (!test_bit(CXL_CM_CAP_CAP_ID_RAS, cxlds->capabilities)) + return rc; + + rc = cxl_map_component_regs(&cxlds->reg_map, + &cxlds->regs.component, + BIT(CXL_CM_CAP_CAP_ID_RAS)); + if (rc) + dev_dbg(&pdev->dev, "Failed to map RAS capability.\n"); + + return rc; +} +EXPORT_SYMBOL_NS_GPL(cxl_pci_accel_setup_regs, "CXL"); + int cxl_pci_get_bandwidth(struct pci_dev *pdev, struct access_coordinate *c) { int speed, bw; diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h index 464e5fb006ba..c1bb0359476c 100644 --- a/include/cxl/cxl.h +++ b/include/cxl/cxl.h @@ -43,4 +43,6 @@ int cxl_set_resource(struct cxl_dev_state *cxlds, struct resource res, bool cxl_pci_check_caps(struct cxl_dev_state *cxlds, unsigned long *expected_caps, unsigned long *current_caps); +struct pci_dev; +int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_dev_state *cxlds); #endif