| Message ID | 20250120030947.254930-3-lizhijian@fujitsu.com |
|---|---|
| State | New |
| Headers | show |
| Series | [1/3] hw/mem/cxl_type3: Add paired msix_uninit_exclusive_bar() call | expand |
On Mon, 20 Jan 2025 11:09:47 +0800 Li Zhijian <lizhijian@fujitsu.com> wrote: > Simply pass the errp to its callee which will set errp if needed, to > enhance error reporting for CXL Type 3 device initialization by setting > the errp when realization functions fail. > > Previously, failing to set `errp` could result in errors being overlooked, > causing the system to mistakenly treat failure scenarios as successful and > potentially leading to redundant cleanup operations in ct3_exit(). > > Signed-off-by: Li Zhijian <lizhijian@fujitsu.com> Looks good to me so just that reordering issue in patch 2. Thanks for fixing this up. Jonathan > --- > hw/mem/cxl_type3.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c > index 9eb3d0979cf5..c3b6a1d6a612 100644 > --- a/hw/mem/cxl_type3.c > +++ b/hw/mem/cxl_type3.c > @@ -883,7 +883,7 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp) > &ct3d->cxl_dstate.device_registers); > > /* MSI(-X) Initialization */ > - rc = msix_init_exclusive_bar(pci_dev, CXL_T3_MSIX_VECTOR_NR, 4, NULL); > + rc = msix_init_exclusive_bar(pci_dev, CXL_T3_MSIX_VECTOR_NR, 4, errp); > if (rc) { > goto err_free_special_ops; > } > @@ -904,7 +904,7 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp) > > pcie_cap_deverr_init(pci_dev); > /* Leave a bit of room for expansion */ > - rc = pcie_aer_init(pci_dev, PCI_ERR_VER, 0x200, PCI_ERR_SIZEOF, NULL); > + rc = pcie_aer_init(pci_dev, PCI_ERR_VER, 0x200, PCI_ERR_SIZEOF, errp); > if (rc) { > goto err_release_cdat; > }
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index 9eb3d0979cf5..c3b6a1d6a612 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -883,7 +883,7 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp) &ct3d->cxl_dstate.device_registers); /* MSI(-X) Initialization */ - rc = msix_init_exclusive_bar(pci_dev, CXL_T3_MSIX_VECTOR_NR, 4, NULL); + rc = msix_init_exclusive_bar(pci_dev, CXL_T3_MSIX_VECTOR_NR, 4, errp); if (rc) { goto err_free_special_ops; } @@ -904,7 +904,7 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp) pcie_cap_deverr_init(pci_dev); /* Leave a bit of room for expansion */ - rc = pcie_aer_init(pci_dev, PCI_ERR_VER, 0x200, PCI_ERR_SIZEOF, NULL); + rc = pcie_aer_init(pci_dev, PCI_ERR_VER, 0x200, PCI_ERR_SIZEOF, errp); if (rc) { goto err_release_cdat; }
Simply pass the errp to its callee which will set errp if needed, to enhance error reporting for CXL Type 3 device initialization by setting the errp when realization functions fail. Previously, failing to set `errp` could result in errors being overlooked, causing the system to mistakenly treat failure scenarios as successful and potentially leading to redundant cleanup operations in ct3_exit(). Signed-off-by: Li Zhijian <lizhijian@fujitsu.com> --- hw/mem/cxl_type3.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)