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(unknown [10.167.135.44]) by edo.cn.fujitsu.com (Postfix) with ESMTP id 6B1111A0071; Mon, 20 Jan 2025 11:09:56 +0800 (CST) From: Li Zhijian To: qemu-devel@nongnu.org Cc: Jonathan Cameron , Fan Ni , linux-cxl@vger.kernel.org, Li Zhijian Subject: [PATCH 3/3] hw/mem/cxl_type3: Ensure errp is set on realization failure Date: Mon, 20 Jan 2025 11:09:47 +0800 Message-Id: <20250120030947.254930-3-lizhijian@fujitsu.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20250120030947.254930-1-lizhijian@fujitsu.com> References: <20250120030947.254930-1-lizhijian@fujitsu.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-TM-AS-Product-Ver: IMSS-9.1.0.1417-9.0.0.1002-28934.004 X-TM-AS-User-Approved-Sender: Yes X-TMASE-Version: IMSS-9.1.0.1417-9.0.1002-28934.004 X-TMASE-Result: 10-2.571100-10.000000 X-TMASE-MatchedRID: DVe2RIcZexn+iwYk8es7vxFbgtHjUWLy2FA7wK9mP9dULhp+W/a9mb8F Hrw7frluf146W0iUu2tMCgkc3/BmTUwYXRRr2ymnzr16YOzjZ126hgVvSdGKo5NciW4ks8ZLbf4 4QeBkGfvi8zVgXoAltuJ5hXsnxp7jC24oEZ6SpSmcfuxsiY4QFP2uYHfvH0BeyPnbtDEL25Nc5N vwi7UFuJWuTH306ghoOV8kmsf1pLOGjucNK4EBjs3VrL4N2KveoBg/1GfUNgr5rOGgS9jIc5sNE GpLafrrLM/nEDLP056e+TDiyH/49wxfkLAfkNNSaAZk0sEcY14= X-TMASE-SNAP-Result: 1.821001.0001-0-1-22:0,33:0,34:0-0 Simply pass the errp to its callee which will set errp if needed, to enhance error reporting for CXL Type 3 device initialization by setting the errp when realization functions fail. Previously, failing to set `errp` could result in errors being overlooked, causing the system to mistakenly treat failure scenarios as successful and potentially leading to redundant cleanup operations in ct3_exit(). Signed-off-by: Li Zhijian --- hw/mem/cxl_type3.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index 9eb3d0979cf5..c3b6a1d6a612 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -883,7 +883,7 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp) &ct3d->cxl_dstate.device_registers); /* MSI(-X) Initialization */ - rc = msix_init_exclusive_bar(pci_dev, CXL_T3_MSIX_VECTOR_NR, 4, NULL); + rc = msix_init_exclusive_bar(pci_dev, CXL_T3_MSIX_VECTOR_NR, 4, errp); if (rc) { goto err_free_special_ops; } @@ -904,7 +904,7 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp) pcie_cap_deverr_init(pci_dev); /* Leave a bit of room for expansion */ - rc = pcie_aer_init(pci_dev, PCI_ERR_VER, 0x200, PCI_ERR_SIZEOF, NULL); + rc = pcie_aer_init(pci_dev, PCI_ERR_VER, 0x200, PCI_ERR_SIZEOF, errp); if (rc) { goto err_release_cdat; }