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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SJ5PEPF000001E9.mail.protection.outlook.com (10.167.242.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8445.10 via Frontend Transport; Tue, 11 Feb 2025 19:25:46 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 11 Feb 2025 13:25:45 -0600 From: Terry Bowman To: , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v7 05/17] PCI/AER: Add CXL PCIe Port correctable error support in AER service driver Date: Tue, 11 Feb 2025 13:24:32 -0600 Message-ID: <20250211192444.2292833-6-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250211192444.2292833-1-terry.bowman@amd.com> References: <20250211192444.2292833-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001E9:EE_|SA1PR12MB8841:EE_ X-MS-Office365-Filtering-Correlation-Id: 043a93d3-b081-4e2b-a178-08dd4ad1e2d0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|82310400026|36860700013|1800799024|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Feb 2025 19:25:46.8078 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 043a93d3-b081-4e2b-a178-08dd4ad1e2d0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001E9.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8841 The AER service driver supports handling Downstream Port Protocol Errors in Restricted CXL host (RCH) mode also known as CXL1.1. It needs the same functionality for CXL PCIe Ports operating in Virtual Hierarchy (VH) mode.[1] CXL and PCIe Protocol Error handling have different requirements that necessitate a separate handling path. The AER service driver may try to recover PCIe uncorrectable non-fatal errors (UCE). The same recovery is not suitable for CXL PCIe Port devices because of potential for system memory corruption. Instead, CXL Protocol Error handling must use a kernel panic in the case of a fatal or non-fatal UCE. The AER driver's PCIe Protocol Error handling does not panic the kernel in response to a UCE. Introduce a separate path for CXL Protocol Error handling in the AER service driver. This will allow CXL Protocol Errors to use CXL specific handling instead of PCIe handling. Add the CXL specific changes without affecting or adding functionality in the PCIe handling. Make this update alongside the existing Downstream Port RCH error handling logic, extending support to CXL PCIe Ports in VH mode. Remove is_internal_error(). is_internal_error() was used to determine if an AER error was a CXL error. Instead, now rely on pcie_is_cxl_port() to indicate the error is a CXL error. The uncorrectable error (UCE) handling will be added in a future patch. [1] CXL 3.1 Spec, 12.2.2 CXL Root Ports, Downstream Switch Ports, and Upstream Switch Ports Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron Reviewed-by: Dave Jiang Reviewed-by: Ira Weiny Acked-by: Bjorn Helgaas --- drivers/pci/pcie/aer.c | 47 ++++++++++++++++++++++++++++-------------- 1 file changed, 32 insertions(+), 15 deletions(-) diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index f99a1c6fb274..34ec0958afff 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -989,14 +989,6 @@ static bool cxl_error_is_native(struct pci_dev *dev) return (pcie_ports_native || host->native_aer); } -static bool is_internal_error(struct aer_err_info *info) -{ - if (info->severity == AER_CORRECTABLE) - return info->status & PCI_ERR_COR_INTERNAL; - - return info->status & PCI_ERR_UNC_INTN; -} - static int cxl_rch_handle_error_iter(struct pci_dev *dev, void *data) { struct aer_err_info *info = (struct aer_err_info *)data; @@ -1033,9 +1025,23 @@ static void cxl_handle_error(struct pci_dev *dev, struct aer_err_info *info) * RCH's downstream port. Check and handle them in the CXL.mem * device driver. */ - if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_EC && - is_internal_error(info)) - pcie_walk_rcec(dev, cxl_rch_handle_error_iter, info); + if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_EC) + return pcie_walk_rcec(dev, cxl_rch_handle_error_iter, info); + + if (info->severity == AER_CORRECTABLE) { + struct pci_driver *pdrv = dev->driver; + int aer = dev->aer_cap; + + if (aer) + pci_write_config_dword(dev, aer + PCI_ERR_COR_STATUS, + info->status); + + if (pdrv && pdrv->cxl_err_handler && + pdrv->cxl_err_handler->cor_error_detected) + pdrv->cxl_err_handler->cor_error_detected(dev); + + pcie_clear_device_status(dev); + } } static int handles_cxl_error_iter(struct pci_dev *dev, void *data) @@ -1053,9 +1059,13 @@ static bool handles_cxl_errors(struct pci_dev *dev) { bool handles_cxl = false; - if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_EC && - pcie_aer_is_native(dev)) + if (!pcie_aer_is_native(dev)) + return false; + + if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_EC) pcie_walk_rcec(dev, handles_cxl_error_iter, &handles_cxl); + else + handles_cxl = pcie_is_cxl_port(dev); return handles_cxl; } @@ -1073,6 +1083,10 @@ static void cxl_enable_internal_errors(struct pci_dev *dev) static inline void cxl_enable_internal_errors(struct pci_dev *dev) { } static inline void cxl_handle_error(struct pci_dev *dev, struct aer_err_info *info) { } +static bool handles_cxl_errors(struct pci_dev *dev) +{ + return false; +} #endif /** @@ -1110,8 +1124,11 @@ static void pci_aer_handle_error(struct pci_dev *dev, struct aer_err_info *info) static void handle_error_source(struct pci_dev *dev, struct aer_err_info *info) { - cxl_handle_error(dev, info); - pci_aer_handle_error(dev, info); + if (handles_cxl_errors(dev)) + cxl_handle_error(dev, info); + else + pci_aer_handle_error(dev, info); + pci_dev_put(dev); }