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Mon, 31 Mar 2025 09:46:28 -0500 From: To: , , , , , , , , CC: Alejandro Lucero , Ben Cheatham Subject: [PATCH v12 13/23] cxl: define a driver interface for DPA allocation Date: Mon, 31 Mar 2025 15:45:45 +0100 Message-ID: <20250331144555.1947819-14-alejandro.lucero-palau@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250331144555.1947819-1-alejandro.lucero-palau@amd.com> References: <20250331144555.1947819-1-alejandro.lucero-palau@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343E:EE_|IA1PR12MB9466:EE_ X-MS-Office365-Filtering-Correlation-Id: 425f3e0c-5f71-4c9b-994d-08dd7062d2e2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|34020700016|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: r8bhUmf8zCsbWAAUmvgtBVWpj8FbZ7FgTLWsR5xUnHPhrDnUCpWsszdRZg1854Q3xM3h4edEBSZ7NiSoAhEKX7Jn841UIN7bKJlyaAosAnWchVz/U0s7UbvETURW1Dsc9Ku9Pf1hX0TD6C7TofLeelLvMiVi0LaCxOQFdVOInJDaX4baD20bIx+QchfnGbCTegLPDYMwf/tVHEKcvcZWConpkSN2WrwmQqPqj98I0ve76UcQ9HvNdVbPq1dCQaZw0OJhNNzma2g06fGqyQXskSgD0ch+Oeiy4cH5KDWOXXTm+Kb4S+gS2PqWzJpk/YZVCt7OOxQ/J2bMaIjiFP56FCh+GpQPeTIrwptYvC81yGnYIQeX//XfFDcTzD7p+Pd0MzBvyxU2tWFasd2UvifJYKkZz9MUUT0Vhdk6eIL5hOVargkgJaJbq0GHVfiN/LMAu5oC8Z8A85qTsZkavFOn5Rj80srJdExZOvejM8tOUkd50vxYqlelE2nIUYo9MGYKPkH6bIbghR7k/ZWtY9RDTRlaYQYvJEKU9y3Fd+zZ1/pG6I/BVPfRvozkcgqkZZR7LaJOjwCPd0AXvmKZJrJhZIjsUG32SiUinQpYvLW3psMEhkzstsfV44lJDmM2qGf77Q40Kvo3xRkZuIadRniW43EX92UadWm2B5BrFK8Il5+BciXmW3bH5TzVWzZruFTSqxclwvCzEkVAmE9lLXRcEhEijUGheLuAzG77kLQkLtEOUQXP/CycdZqvov7qupquWr5OjY3u6DxWoyzifx1LGAvDn8aJNZtyVbjbIwKCf73Vc0Jvk9VKo5UGDr1YBtka7oopNvcneR5kyD99UAR+jMtvYV35qsHIL7QamWxqcBkHKoQCSLod59siAjluA6SBY3wBNBsr53nFU3dqJZsadUrF+q1Qcvyk785PiniMJLcX9SLOYnA0pIGCddoXLQNFzK08rI60SDTTLuS0EDxAsz7N9V9sVTitFGA2yamp3b8+1NMJFkYgMyY8nwU169WgvHJ24l/FrqcJjxIV9S3JRCShinfWra/HDGe3N4rU6KFd3b0+UVWspPUe69cO9PtKeXcOtNqkn5L4D8iOC/m9ELNPiGLXXpcKyD+BcnT9FsByyzKhw4sWtLRG/rbPshv8y00/QzlofdQAgfGvbI/WFj5rk/aFYV/DEe6DHiloe/I7MynaD9uOK57RGBUT199gWPo9tsnHKPCXfqbwQgPFJdCbdLSmoKEUMeh3RafcWFSSkbQ0dVsYCFMelJaBkxVoR2OwSBa+iioRT8W2QAasgqGtRozg+yxOdoDgfS88+EtSlkkZbLcxrZeT2T1bA7k1I30RIG6V4IEh29eiF2cr7XZ6/mgFz8l3jnxUkoT6l77Xkm+TSQSYl/SePF1GDqb0M8PXjAp8WBeQrvKvGcSb5VdJHVvJqpC8exwWRXKOobBNy6+6AdZz5gKBZVf5REWdC7EWNJqvewpM16eGlzwnWzHERwWkAqi2PkFateOPU48= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(376014)(34020700016)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Mar 2025 14:46:30.2712 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 425f3e0c-5f71-4c9b-994d-08dd7062d2e2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB9466 From: Alejandro Lucero Region creation involves finding available DPA (device-physical-address) capacity to map into HPA (host-physical-address) space. Define an API, cxl_request_dpa(), that tries to allocate the DPA memory the driver requires to operate. The memory requested should not be bigger than the max available HPA obtained previously with cxl_get_hpa_freespace. Based on https://lore.kernel.org/linux-cxl/168592158743.1948938.7622563891193802610.stgit@dwillia2-xfh.jf.intel.com/ Signed-off-by: Alejandro Lucero Reviewed-by: Ben Cheatham --- drivers/cxl/core/hdm.c | 83 ++++++++++++++++++++++++++++++++++++++++++ include/cxl/cxl.h | 5 +++ 2 files changed, 88 insertions(+) diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c index 70cae4ebf8a4..db6d99e07d45 100644 --- a/drivers/cxl/core/hdm.c +++ b/drivers/cxl/core/hdm.c @@ -3,6 +3,7 @@ #include #include #include +#include #include "cxlmem.h" #include "core.h" @@ -572,6 +573,7 @@ int cxl_dpa_free(struct cxl_endpoint_decoder *cxled) devm_cxl_dpa_release(cxled); return 0; } +EXPORT_SYMBOL_NS_GPL(cxl_dpa_free, "CXL"); int cxl_dpa_set_part(struct cxl_endpoint_decoder *cxled, enum cxl_partition_mode mode) @@ -686,6 +688,87 @@ int cxl_dpa_alloc(struct cxl_endpoint_decoder *cxled, unsigned long long size) return devm_add_action_or_reset(&port->dev, cxl_dpa_release, cxled); } +static int find_free_decoder(struct device *dev, const void *data) +{ + struct cxl_endpoint_decoder *cxled; + struct cxl_port *port; + + if (!is_endpoint_decoder(dev)) + return 0; + + cxled = to_cxl_endpoint_decoder(dev); + port = cxled_to_port(cxled); + + if (cxled->cxld.id != port->hdm_end + 1) + return 0; + + return 1; +} + +/** + * cxl_request_dpa - search and reserve DPA given input constraints + * @cxlmd: memdev with an endpoint port with available decoders + * @is_ram: DPA operation mode (ram vs pmem) + * @alloc: dpa size required + * + * Given that a region needs to allocate from limited HPA capacity it + * may be the case that a device has more mappable DPA capacity than + * available HPA. The expectation is that @alloc is a driver known + * value based on the device capacity but it could not be available + * due to HPA constraints. + * + * Returns a pinned cxl_decoder with at least @alloc bytes of capacity + * reserved, or an error pointer. The caller is also expected to own the + * lifetime of the memdev registration associated with the endpoint to + * pin the decoder registered as well. + */ +struct cxl_endpoint_decoder *cxl_request_dpa(struct cxl_memdev *cxlmd, + bool is_ram, + resource_size_t alloc) +{ + struct cxl_port *endpoint = cxlmd->endpoint; + struct cxl_endpoint_decoder *cxled; + enum cxl_partition_mode mode; + struct device *cxled_dev; + int rc; + + if (!IS_ALIGNED(alloc, SZ_256M)) + return ERR_PTR(-EINVAL); + + down_read(&cxl_dpa_rwsem); + cxled_dev = device_find_child(&endpoint->dev, NULL, find_free_decoder); + up_read(&cxl_dpa_rwsem); + + if (!cxled_dev) + return ERR_PTR(-ENXIO); + + cxled = to_cxl_endpoint_decoder(cxled_dev); + + if (!cxled) { + rc = -ENODEV; + goto err; + } + + if (is_ram) + mode = CXL_PARTMODE_RAM; + else + mode = CXL_PARTMODE_PMEM; + + rc = cxl_dpa_set_part(cxled, mode); + if (rc) + goto err; + + rc = cxl_dpa_alloc(cxled, alloc); + if (rc) + goto err; + + return cxled; +err: + put_device(cxled_dev); + return ERR_PTR(rc); +} +EXPORT_SYMBOL_NS_GPL(cxl_request_dpa, "CXL"); + static void cxld_set_interleave(struct cxl_decoder *cxld, u32 *ctrl) { u16 eig; diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h index a098b4e26980..22061646b147 100644 --- a/include/cxl/cxl.h +++ b/include/cxl/cxl.h @@ -7,6 +7,7 @@ #include #include #include +#include #include /* @@ -256,4 +257,8 @@ struct cxl_root_decoder *cxl_get_hpa_freespace(struct cxl_memdev *cxlmd, unsigned long flags, resource_size_t *max); void cxl_put_root_decoder(struct cxl_root_decoder *cxlrd); +struct cxl_endpoint_decoder *cxl_request_dpa(struct cxl_memdev *cxlmd, + bool is_ram, + resource_size_t alloc); +int cxl_dpa_free(struct cxl_endpoint_decoder *cxled); #endif