| Message ID | 20250331144555.1947819-6-alejandro.lucero-palau@amd.com |
|---|---|
| State | New |
| Headers | show |
| Series | cxl: add type2 device basic support | expand |
On Mon, Mar 31, 2025 at 03:45:37PM +0100, alejandro.lucero-palau@amd.com wrote: > From: Alejandro Lucero <alucerop@amd.com> > > Create a new function for a type2 device initialising > cxl_dev_state struct regarding cxl regs setup and mapping. > > Export the capabilities found for checking them against the > expected ones by the driver. > > Signed-off-by: Alejandro Lucero <alucerop@amd.com> > Reviewed-by: Ben Cheatham <benjamin.cheatham@amd.com> > --- > drivers/cxl/core/pci.c | 52 ++++++++++++++++++++++++++++++++++++++++++ > include/cxl/cxl.h | 5 ++++ > 2 files changed, 57 insertions(+) > > diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c > index 05399292209a..e48320e16a4f 100644 > --- a/drivers/cxl/core/pci.c > +++ b/drivers/cxl/core/pci.c > @@ -1095,6 +1095,58 @@ int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, > } > EXPORT_SYMBOL_NS_GPL(cxl_pci_setup_regs, "CXL"); > > +static int cxl_pci_setup_memdev_regs(struct pci_dev *pdev, > + struct cxl_dev_state *cxlds, > + unsigned long *caps) > +{ > + struct cxl_register_map map; > + int rc; > + > + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map, caps); > + /* > + * This call can return -ENODEV if regs not found. This is not an error > + * for Type2 since these regs are not mandatory. If they do exist then > + * mapping them should not fail. If they should exist, it is with driver > + * calling cxl_pci_check_caps where the problem should be found. > + */ > + if (rc == -ENODEV) > + return 0; > + > + if (rc) > + return rc; > + > + return cxl_map_device_regs(&map, &cxlds->regs.device_regs); > +} > + > +int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_dev_state *cxlds, > + unsigned long *caps) nit: the indentation of the line above is not quite aligned to the inside of the opening parentheses on the previous line. There is one space too many. ...
diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 05399292209a..e48320e16a4f 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -1095,6 +1095,58 @@ int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, } EXPORT_SYMBOL_NS_GPL(cxl_pci_setup_regs, "CXL"); +static int cxl_pci_setup_memdev_regs(struct pci_dev *pdev, + struct cxl_dev_state *cxlds, + unsigned long *caps) +{ + struct cxl_register_map map; + int rc; + + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map, caps); + /* + * This call can return -ENODEV if regs not found. This is not an error + * for Type2 since these regs are not mandatory. If they do exist then + * mapping them should not fail. If they should exist, it is with driver + * calling cxl_pci_check_caps where the problem should be found. + */ + if (rc == -ENODEV) + return 0; + + if (rc) + return rc; + + return cxl_map_device_regs(&map, &cxlds->regs.device_regs); +} + +int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_dev_state *cxlds, + unsigned long *caps) +{ + int rc; + + rc = cxl_pci_setup_memdev_regs(pdev, cxlds, caps); + if (rc) + return rc; + + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, + &cxlds->reg_map, caps); + if (rc) { + dev_warn(&pdev->dev, "No component registers (%d)\n", rc); + return rc; + } + + if (!caps || !test_bit(CXL_CM_CAP_CAP_ID_RAS, caps)) + return 0; + + rc = cxl_map_component_regs(&cxlds->reg_map, + &cxlds->regs.component, + BIT(CXL_CM_CAP_CAP_ID_RAS)); + if (rc) + dev_dbg(&pdev->dev, "Failed to map RAS capability.\n"); + + return rc; +} +EXPORT_SYMBOL_NS_GPL(cxl_pci_accel_setup_regs, "CXL"); + int cxl_pci_get_bandwidth(struct pci_dev *pdev, struct access_coordinate *c) { int speed, bw; diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h index b9cd98950a38..a3cbf3a620e4 100644 --- a/include/cxl/cxl.h +++ b/include/cxl/cxl.h @@ -226,4 +226,9 @@ struct cxl_dev_state *_cxl_dev_state_create(struct device *dev, (drv_struct *)_cxl_dev_state_create(parent, type, serial, dvsec, \ sizeof(drv_struct), mbox); \ }) + +struct pci_dev; +struct cxl_memdev_state; +int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_dev_state *cxlmds, + unsigned long *caps); #endif