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Mon, 31 Mar 2025 09:46:19 -0500 From: To: , , , , , , , , CC: Alejandro Lucero , Ben Cheatham Subject: [PATCH v12 07/23] cxl: support dpa initialization without a mailbox Date: Mon, 31 Mar 2025 15:45:39 +0100 Message-ID: <20250331144555.1947819-8-alejandro.lucero-palau@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250331144555.1947819-1-alejandro.lucero-palau@amd.com> References: <20250331144555.1947819-1-alejandro.lucero-palau@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Received-SPF: None (SATLEXMB05.amd.com: alejandro.lucero-palau@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015C7:EE_|MW3PR12MB4492:EE_ X-MS-Office365-Filtering-Correlation-Id: 9a121882-e21b-44cf-f590-08dd7062d141 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|34020700016|36860700013|82310400026; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Mar 2025 14:46:27.5251 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9a121882-e21b-44cf-f590-08dd7062d141 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015C7.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4492 From: Alejandro Lucero Type3 relies on mailbox CXL_MBOX_OP_IDENTIFY command for initializing memdev state params which end up being used for dma initialization. Allow a Type2 driver to initialize dpa simply by giving the size of its volatile and/or non-volatile hardware partitions. Export cxl_dpa_setup as well for initializing those added dpa partitions with the proper resources. Signed-off-by: Alejandro Lucero Reviewed-by: Ben Cheatham --- drivers/cxl/core/mbox.c | 17 ++++++++++++++--- drivers/cxl/cxlmem.h | 13 ------------- include/cxl/cxl.h | 14 ++++++++++++++ 3 files changed, 28 insertions(+), 16 deletions(-) diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c index ab994d459f46..e4610e778723 100644 --- a/drivers/cxl/core/mbox.c +++ b/drivers/cxl/core/mbox.c @@ -1284,6 +1284,18 @@ static void add_part(struct cxl_dpa_info *info, u64 start, u64 size, enum cxl_pa info->nr_partitions++; } +void cxl_mem_dpa_init(struct cxl_dpa_info *info, u64 volatile_bytes, + u64 persistent_bytes) +{ + if (!info->size) + info->size = volatile_bytes + persistent_bytes; + + add_part(info, 0, volatile_bytes, CXL_PARTMODE_RAM); + add_part(info, volatile_bytes, persistent_bytes, + CXL_PARTMODE_PMEM); +} +EXPORT_SYMBOL_NS_GPL(cxl_mem_dpa_init, "CXL"); + int cxl_mem_dpa_fetch(struct cxl_memdev_state *mds, struct cxl_dpa_info *info) { struct cxl_dev_state *cxlds = &mds->cxlds; @@ -1298,9 +1310,8 @@ int cxl_mem_dpa_fetch(struct cxl_memdev_state *mds, struct cxl_dpa_info *info) info->size = mds->total_bytes; if (mds->partition_align_bytes == 0) { - add_part(info, 0, mds->volatile_only_bytes, CXL_PARTMODE_RAM); - add_part(info, mds->volatile_only_bytes, - mds->persistent_only_bytes, CXL_PARTMODE_PMEM); + cxl_mem_dpa_init(info, mds->volatile_only_bytes, + mds->persistent_only_bytes); return 0; } diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h index e7cd31b9f107..e47f51025efd 100644 --- a/drivers/cxl/cxlmem.h +++ b/drivers/cxl/cxlmem.h @@ -98,19 +98,6 @@ int devm_cxl_dpa_reserve(struct cxl_endpoint_decoder *cxled, resource_size_t base, resource_size_t len, resource_size_t skipped); -#define CXL_NR_PARTITIONS_MAX 2 - -struct cxl_dpa_info { - u64 size; - struct cxl_dpa_part_info { - struct range range; - enum cxl_partition_mode mode; - } part[CXL_NR_PARTITIONS_MAX]; - int nr_partitions; -}; - -int cxl_dpa_setup(struct cxl_dev_state *cxlds, const struct cxl_dpa_info *info); - static inline struct cxl_ep *cxl_ep_load(struct cxl_port *port, struct cxl_memdev *cxlmd) { diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h index a3cbf3a620e4..74f03773baed 100644 --- a/include/cxl/cxl.h +++ b/include/cxl/cxl.h @@ -213,6 +213,17 @@ struct cxl_dev_state { #endif }; +#define CXL_NR_PARTITIONS_MAX 2 + +struct cxl_dpa_info { + u64 size; + struct cxl_dpa_part_info { + struct range range; + enum cxl_partition_mode mode; + } part[CXL_NR_PARTITIONS_MAX]; + int nr_partitions; +}; + struct cxl_dev_state *_cxl_dev_state_create(struct device *dev, enum cxl_devtype type, u64 serial, u16 dvsec, size_t size, @@ -231,4 +242,7 @@ struct pci_dev; struct cxl_memdev_state; int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_dev_state *cxlmds, unsigned long *caps); +void cxl_mem_dpa_init(struct cxl_dpa_info *info, u64 volatile_bytes, + u64 persistent_bytes); +int cxl_dpa_setup(struct cxl_dev_state *cxlds, const struct cxl_dpa_info *info); #endif