From patchwork Fri Oct 5 13:08:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sharat Masetty X-Patchwork-Id: 10628017 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 520591515 for ; Fri, 5 Oct 2018 13:08:48 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3E055290F3 for ; Fri, 5 Oct 2018 13:08:48 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3235429104; Fri, 5 Oct 2018 13:08:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D9531290F3 for ; Fri, 5 Oct 2018 13:08:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E76286E7FB; Fri, 5 Oct 2018 13:08:46 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from smtp.codeaurora.org (smtp.codeaurora.org [198.145.29.96]) by gabe.freedesktop.org (Postfix) with ESMTPS id 115146E7F2; Fri, 5 Oct 2018 13:08:45 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1000) id E4EA160818; Fri, 5 Oct 2018 13:08:44 +0000 (UTC) Received: from smasetty-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: smasetty@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id C805F6079B; Fri, 5 Oct 2018 13:08:42 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org C805F6079B From: Sharat Masetty To: freedreno@lists.freedesktop.org Subject: [v2 0/7] drm/msm/a6xx: System Cache Support Date: Fri, 5 Oct 2018 18:38:28 +0530 Message-Id: <1538744915-25490-1-git-send-email-smasetty@codeaurora.org> X-Mailer: git-send-email 1.9.1 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-msm@vger.kernel.org, Sharat Masetty , dri-devel@lists.freedesktop.org MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Some hardware variants contain a system level cache or the last level cache(llc). This cache is typically a large block which is shared by multiple clients on the SOC. GPU uses the system cache to cache both the GPU data buffers(like textures) as well the SMMU pagetables. This helps with improved render performance as well as lower power consumption by reducing the bus traffic to the system memory. The system cache architecture allows the cache to be split into slices which then be used by multiple SOC clients. This patch series is an effort to enable and use two of those slices perallocated for the GPU, one for the GPU data buffers and another for the GPU SMMU hardware pagetables. v2: Fixed code review comments from previous round. The first version was posted a few months ago, so this is a refresh of the previous series. Update code to conform to the newer version of the core llcc driver. Minor tweaks and adjustments here and there. Testing: Nothing breaks, but need to profile DDR traffic to see the impact the cache blocks are really making. Please review... Jordan Crouse (1): soc: qcom: llcc-slice: Add error checks for API functions Sharat Masetty (5): drm/msm: rearrange the gpu_rmw() function drm/msm/adreno: Add registers in the GPU CX domain arm64:dts:sdm845: Add register range for gpu CX drm/msm: Pass mmu features to generic layers drm/msm/a6xx: Add support for using system cache(LLC) Vivek Gautam (1): iommu/arm-smmu: Add support to use Last level cache arch/arm64/boot/dts/qcom/sdm845.dtsi | 4 +- drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a6xx.xml.h | 3 + drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 159 +++++++++++++++++++++++++++++++- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 9 ++ drivers/gpu/drm/msm/adreno/adreno_gpu.c | 4 +- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 +- drivers/gpu/drm/msm/msm_drv.c | 8 ++ drivers/gpu/drm/msm/msm_drv.h | 1 + drivers/gpu/drm/msm/msm_gpu.c | 6 +- drivers/gpu/drm/msm/msm_gpu.h | 6 +- drivers/gpu/drm/msm/msm_iommu.c | 13 +++ drivers/gpu/drm/msm/msm_mmu.h | 14 +++ drivers/iommu/arm-smmu.c | 14 +++ drivers/iommu/io-pgtable-arm.c | 24 ++++- drivers/iommu/io-pgtable.h | 4 + drivers/soc/qcom/llcc-slice.c | 15 ++- include/linux/iommu.h | 4 + 20 files changed, 276 insertions(+), 20 deletions(-) --- 1.9.1