| Message ID | 20180927114850.24565-1-jagan@amarulasolutions.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | drm/sun4i: Allwinner A64 MIPI-DSI support | expand |
On Thu, Sep 27, 2018 at 10:28 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote: > > On Thu, Sep 27, 2018 at 05:18:45PM +0530, Jagan Teki wrote: > > TCON DRQ set bits for non-burst DSI mode can computed via > > horizontal front porch instead of front porch + sync timings. > > > > Since there no documentation for TCON_DRQ_REG(0x7c) register > > this change is taken as reference from BPI-M64-bsp. > > Detailing more what the issue is would be great. > > > Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> > > --- > > drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c > > index 599284971ab6..9918fdb990ff 100644 > > --- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c > > +++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c > > @@ -367,9 +367,9 @@ static void sun6i_dsi_setup_burst(struct sun6i_dsi *dsi, > > struct mipi_dsi_device *device = dsi->device; > > u32 val = 0; > > The computation here is in the A64 driver: > > if ((panel->lcd_ht - panel->lcd_x - panel->lcd_hbp) < 21) { > dsi_dev[sel]->dsi_tcon_drq.bits.drq_mode = 0; > } else { > dsi_dev[sel]->dsi_tcon_drq.bits.drq_set = > (panel->lcd_ht-panel->lcd_x-panel->lcd_hbp-20) * > dsi_pixel_bits[panel->lcd_dsi_format]/(8*4); > } > > It is testing that the sync + front porch is smaller than 21, and > otherwise sets the drq. > > > - if ((mode->hsync_end - mode->hdisplay) > 20) { > > My code here is testing that the difference between hsync_end and > hdisplay is superior to 20, and sets the DRQ if true. The condition is > reversed, but otherwise, that difference is the front porch plus the > sync length. True, I understand this, but does drq setting here is specific to SoC? I thought of finding DRQ in A31 BSP but I couldn't find the code. do you have bsp somewhere in github? > > > + if ((mode->hsync_start - mode->hdisplay) > 20) { > > However, you are testing for just the front porch, unlike what your > commit log is saying, and unlike what allwinner's code is saying. So > this deserves some explanation. but A64 is doing this, do you think it's completely A64 specific or testing panel with front porch drq?
On Thu, Sep 27, 2018 at 11:15:50PM +0530, Jagan Teki wrote: > On Thu, Sep 27, 2018 at 10:28 PM Maxime Ripard > <maxime.ripard@bootlin.com> wrote: > > > > On Thu, Sep 27, 2018 at 05:18:45PM +0530, Jagan Teki wrote: > > > TCON DRQ set bits for non-burst DSI mode can computed via > > > horizontal front porch instead of front porch + sync timings. > > > > > > Since there no documentation for TCON_DRQ_REG(0x7c) register > > > this change is taken as reference from BPI-M64-bsp. > > > > Detailing more what the issue is would be great. > > > > > Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> > > > --- > > > drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 4 ++-- > > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c > > > index 599284971ab6..9918fdb990ff 100644 > > > --- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c > > > +++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c > > > @@ -367,9 +367,9 @@ static void sun6i_dsi_setup_burst(struct sun6i_dsi *dsi, > > > struct mipi_dsi_device *device = dsi->device; > > > u32 val = 0; > > > > The computation here is in the A64 driver: > > > > if ((panel->lcd_ht - panel->lcd_x - panel->lcd_hbp) < 21) { > > dsi_dev[sel]->dsi_tcon_drq.bits.drq_mode = 0; > > } else { > > dsi_dev[sel]->dsi_tcon_drq.bits.drq_set = > > (panel->lcd_ht-panel->lcd_x-panel->lcd_hbp-20) * > > dsi_pixel_bits[panel->lcd_dsi_format]/(8*4); > > } > > > > It is testing that the sync + front porch is smaller than 21, and > > otherwise sets the drq. > > > > > - if ((mode->hsync_end - mode->hdisplay) > 20) { > > > > My code here is testing that the difference between hsync_end and > > hdisplay is superior to 20, and sets the DRQ if true. The condition is > > reversed, but otherwise, that difference is the front porch plus the > > sync length. > > True, I understand this, but does drq setting here is specific to SoC? > I thought of finding DRQ in A31 BSP but I couldn't find the code. do > you have bsp somewhere in github? > > > > > > + if ((mode->hsync_start - mode->hdisplay) > 20) { > > > > However, you are testing for just the front porch, unlike what your > > commit log is saying, and unlike what allwinner's code is saying. So > > this deserves some explanation. > > but A64 is doing this, do you think it's completely A64 specific or > testing panel with front porch drq? See the above code excerpt: panel->lcd_ht - panel->lcd_x - panel->lcd_hbp This is hsync + front porch. Not the sole front porch. So no, it's not doing this. Maxime
On Tuesday 02 October 2018 06:50 PM, Maxime Ripard wrote: > On Thu, Sep 27, 2018 at 11:15:50PM +0530, Jagan Teki wrote: >> On Thu, Sep 27, 2018 at 10:28 PM Maxime Ripard >> <maxime.ripard@bootlin.com> wrote: >>> >>> On Thu, Sep 27, 2018 at 05:18:45PM +0530, Jagan Teki wrote: >>>> TCON DRQ set bits for non-burst DSI mode can computed via >>>> horizontal front porch instead of front porch + sync timings. >>>> >>>> Since there no documentation for TCON_DRQ_REG(0x7c) register >>>> this change is taken as reference from BPI-M64-bsp. >>> >>> Detailing more what the issue is would be great. >>> >>>> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> >>>> --- >>>> drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 4 ++-- >>>> 1 file changed, 2 insertions(+), 2 deletions(-) >>>> >>>> diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c >>>> index 599284971ab6..9918fdb990ff 100644 >>>> --- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c >>>> +++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c >>>> @@ -367,9 +367,9 @@ static void sun6i_dsi_setup_burst(struct sun6i_dsi *dsi, >>>> struct mipi_dsi_device *device = dsi->device; >>>> u32 val = 0; >>> >>> The computation here is in the A64 driver: >>> >>> if ((panel->lcd_ht - panel->lcd_x - panel->lcd_hbp) < 21) { >>> dsi_dev[sel]->dsi_tcon_drq.bits.drq_mode = 0; >>> } else { >>> dsi_dev[sel]->dsi_tcon_drq.bits.drq_set = >>> (panel->lcd_ht-panel->lcd_x-panel->lcd_hbp-20) * >>> dsi_pixel_bits[panel->lcd_dsi_format]/(8*4); >>> } >>> >>> It is testing that the sync + front porch is smaller than 21, and >>> otherwise sets the drq. >>> >>>> - if ((mode->hsync_end - mode->hdisplay) > 20) { >>> >>> My code here is testing that the difference between hsync_end and >>> hdisplay is superior to 20, and sets the DRQ if true. The condition is >>> reversed, but otherwise, that difference is the front porch plus the >>> sync length. >> >> True, I understand this, but does drq setting here is specific to SoC? >> I thought of finding DRQ in A31 BSP but I couldn't find the code. do >> you have bsp somewhere in github? >> >>> >>>> + if ((mode->hsync_start - mode->hdisplay) > 20) { >>> >>> However, you are testing for just the front porch, unlike what your >>> commit log is saying, and unlike what allwinner's code is saying. So >>> this deserves some explanation. >> >> but A64 is doing this, do you think it's completely A64 specific or >> testing panel with front porch drq? > > See the above code excerpt: > panel->lcd_ht - panel->lcd_x - panel->lcd_hbp > > This is hsync + front porch. Not the sole front porch. So no, it's not > doing this. => panel->lcd_ht - panel->lcd_x - panel->lcd_hbp from drivers/video/sunxi/disp2/disp/de/disp_lcd.c timmings->hor_front_porch= panel_info->lcd_ht-panel_info->lcd_hbp - panel_info->lcd_x; => (timmings->hor_front_porch + panel->lcd_hbp + panel->lcd_x) - panel->lcd_x - panel->hbp => timmings->hor_front_porch => mode->hsync_start - mode->hdisplay This is simply a front porch.
On Wed, Oct 03, 2018 at 08:52:06AM +0530, Jagan Teki wrote: > On Tuesday 02 October 2018 06:50 PM, Maxime Ripard wrote: > > On Thu, Sep 27, 2018 at 11:15:50PM +0530, Jagan Teki wrote: > > > On Thu, Sep 27, 2018 at 10:28 PM Maxime Ripard > > > <maxime.ripard@bootlin.com> wrote: > > > > > > > > On Thu, Sep 27, 2018 at 05:18:45PM +0530, Jagan Teki wrote: > > > > > TCON DRQ set bits for non-burst DSI mode can computed via > > > > > horizontal front porch instead of front porch + sync timings. > > > > > > > > > > Since there no documentation for TCON_DRQ_REG(0x7c) register > > > > > this change is taken as reference from BPI-M64-bsp. > > > > > > > > Detailing more what the issue is would be great. > > > > > > > > > Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> > > > > > --- > > > > > drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 4 ++-- > > > > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > > > > > > > diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c > > > > > index 599284971ab6..9918fdb990ff 100644 > > > > > --- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c > > > > > +++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c > > > > > @@ -367,9 +367,9 @@ static void sun6i_dsi_setup_burst(struct sun6i_dsi *dsi, > > > > > struct mipi_dsi_device *device = dsi->device; > > > > > u32 val = 0; > > > > > > > > The computation here is in the A64 driver: > > > > > > > > if ((panel->lcd_ht - panel->lcd_x - panel->lcd_hbp) < 21) { > > > > dsi_dev[sel]->dsi_tcon_drq.bits.drq_mode = 0; > > > > } else { > > > > dsi_dev[sel]->dsi_tcon_drq.bits.drq_set = > > > > (panel->lcd_ht-panel->lcd_x-panel->lcd_hbp-20) * > > > > dsi_pixel_bits[panel->lcd_dsi_format]/(8*4); > > > > } > > > > > > > > It is testing that the sync + front porch is smaller than 21, and > > > > otherwise sets the drq. > > > > > > > > > - if ((mode->hsync_end - mode->hdisplay) > 20) { > > > > > > > > My code here is testing that the difference between hsync_end and > > > > hdisplay is superior to 20, and sets the DRQ if true. The condition is > > > > reversed, but otherwise, that difference is the front porch plus the > > > > sync length. > > > > > > True, I understand this, but does drq setting here is specific to SoC? > > > I thought of finding DRQ in A31 BSP but I couldn't find the code. do > > > you have bsp somewhere in github? > > > > > > > > > > > > + if ((mode->hsync_start - mode->hdisplay) > 20) { > > > > > > > > However, you are testing for just the front porch, unlike what your > > > > commit log is saying, and unlike what allwinner's code is saying. So > > > > this deserves some explanation. > > > > > > but A64 is doing this, do you think it's completely A64 specific or > > > testing panel with front porch drq? > > > > See the above code excerpt: > > panel->lcd_ht - panel->lcd_x - panel->lcd_hbp > > > > This is hsync + front porch. Not the sole front porch. So no, it's not > > doing this. > > => panel->lcd_ht - panel->lcd_x - panel->lcd_hbp > > from drivers/video/sunxi/disp2/disp/de/disp_lcd.c > timmings->hor_front_porch= panel_info->lcd_ht-panel_info->lcd_hbp - > panel_info->lcd_x; > > => (timmings->hor_front_porch + panel->lcd_hbp + panel->lcd_x) - > panel->lcd_x - panel->hbp > => timmings->hor_front_porch > => mode->hsync_start - mode->hdisplay > > This is simply a front porch. And this should be in your commit log as well. Maxime
This series add MIPI-DSI support on Allwinner A64. The same A31 controller is reused and tweaked for A64 since the register space for both SoC's look same. The current clock rate (270MHz) with nkm (5,2,11) from PLL_MIPI is unable to work with A64 DSI block. I've tested with few changes to verify desired nkm divider values (1, 2, 5) but with existing nkm divider logic(ccu_nkm_find_best) I'm unable to figure out the desired clock rate, anyone suggestion please let me know here. Bananapi S070WV20-CT16 DSI panel with BPI-M64 board works fine, but will figure out and fix the clock logic in next versions. Thanks, Jagan. Jagan Teki (12): clk: sunxi-ng: a64: Fix gate bit of DSI DPHY drm/sun4i: sun6i_mipi_dsi: Add Allwinner A64 MIPI DSI support dt-bindings: sun6i-dsi: Add compatible for A64 MIPI DSI drm/sun4i: sun6i_mipi_dsi: Enable missing DSI bus clock drm/sun4i: sun6i_mipi_dsi: Add DSI Generic short write 2 param transfer drm/sun4i: sun6i_mipi_dsi: Fix VBP size calculation drm/sun4i: sun6i_mipi_dsi: Fix TCON DRQ set bits drm/sun4i: sun6i_mipi_dsi: Refactor vertical video start delay dt-bindings: panel: Add Bananapi S070WV20-CT16 MIPI-DSI panel bindings drm/panel: Add Bananapi S070WV20-CT16 MIPI-DSI panel driver arm64: dts: allwinner: a64: Add DSI pipeline arm64: dts: allwinner: bananapi-m64: Bananapi S070WV20-CT16 DSI panel .../panel/bananapi,s070wv20-ct16-dsi.txt | 21 ++ .../bindings/display/sunxi/sun6i-dsi.txt | 1 + .../dts/allwinner/sun50i-a64-bananapi-m64.dts | 42 +++ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 44 +++ drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 2 +- drivers/gpu/drm/panel/Kconfig | 9 + drivers/gpu/drm/panel/Makefile | 1 + .../gpu/drm/panel/panel-bananapi-s070wv20.c | 336 ++++++++++++++++++ drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 78 +++- drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h | 5 + 10 files changed, 522 insertions(+), 17 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/panel/bananapi,s070wv20-ct16-dsi.txt create mode 100644 drivers/gpu/drm/panel/panel-bananapi-s070wv20.c