[v8,00/19] DSC enabling remaining patches respin

Message

Navare, Manasi Nov. 2, 2018, 9:31 p.m. UTC

This patch series addresses following comments from the previous
series: https://patchwork.freedesktop.org/series/51916/

- no FEC so should reject DSC on external DP
-> Added this to intel_dp_source_supports_dsc
- get_power_domains() thing wasn't right
-> Fixed the logic

-The potentially user triggerable DRM_ERROR()s have to be
 removed or explained why they can't happen (in which case
 a WARN() would probably be a more clear hint to the reader).
-> Changed DRM_ERROR to DRM_DEBUG_KMS

The intel_dsc_enable() call I definitely would like see
moved into the encoder->per_enable(). No one will think to
look for it in the current location.
-> Moved this to intel_ddi_pre_enable_dp

The i915_modparams.enable_psr change seemed unrelated, but
no idea if it's intentional or not.
-> Removed unintentional changes

And finally there were various style nits that are optional.
But I would recomment doing them since it's trivial stuff and
avoids further churn in the code later.
-> Fixed the nits 

Gaurav K Singh (3):
  drm/i915/dsc: Define & Compute VESA DSC params
  drm/i915/dsc: Compute Rate Control parameters for DSC
  drm/i915/dp: Enable/Disable DSC in DP Sink

Manasi Navare (15):
  drm/dsc: Define Display Stream Compression PPS infoframe
  drm/dsc: Define VESA Display Stream Compression Capabilities
  drm/dsc: Add helpers for DSC picture parameter set infoframes
  drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants
  drm/i915/dp: Add DSC params and DSC config to intel_crtc_state
  drm/i915/dp: Compute DSC pipe config in atomic check
  drm/i915/dp: Do not enable PSR2 if DSC is enabled
  drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI
  drm/i915/dp: Configure i915 Picture parameter Set registers during DSC
    enabling
  drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs
  drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes
  drm/i915/dp: Configure Display stream splitter registers during DSC
    enable
  drm/i915/dp: Disable DSC in source by disabling DSS CTL bits
  drm/i915/dsc: Enable and disable appropriate power wells for VDSC
  drm/i915/dsc: Add Per connector debugfs node for DSC support/enable

Srivatsa, Anusha (1):
  drm/dsc: Define Rate Control values that do not change over
    configurations

 Documentation/gpu/drm-kms-helpers.rst   |   12 +
 drivers/gpu/drm/Makefile                |    2 +-
 drivers/gpu/drm/drm_dsc.c               |  228 +++++
 drivers/gpu/drm/i915/Makefile           |    3 +-
 drivers/gpu/drm/i915/i915_debugfs.c     |   71 +-
 drivers/gpu/drm/i915/i915_drv.h         |    4 +
 drivers/gpu/drm/i915/i915_reg.h         |    1 +
 drivers/gpu/drm/i915/intel_ddi.c        |   17 +
 drivers/gpu/drm/i915/intel_display.c    |   23 +-
 drivers/gpu/drm/i915/intel_display.h    |    4 +-
 drivers/gpu/drm/i915/intel_dp.c         |  191 +++-
 drivers/gpu/drm/i915/intel_dp_mst.c     |    2 +-
 drivers/gpu/drm/i915/intel_drv.h        |   21 +
 drivers/gpu/drm/i915/intel_hdmi.c       |   21 +-
 drivers/gpu/drm/i915/intel_psr.c        |   14 +
 drivers/gpu/drm/i915/intel_runtime_pm.c |    4 +-
 drivers/gpu/drm/i915/intel_vdsc.c       | 1100 +++++++++++++++++++++++
 include/drm/drm_dp_helper.h             |    3 +
 include/drm/drm_dsc.h                   |  485 ++++++++++
 19 files changed, 2174 insertions(+), 32 deletions(-)
 create mode 100644 drivers/gpu/drm/drm_dsc.c
 create mode 100644 drivers/gpu/drm/i915/intel_vdsc.c
 create mode 100644 include/drm/drm_dsc.h