From patchwork Tue Nov 20 18:37:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Navare, Manasi" X-Patchwork-Id: 10691055 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7F5A016B1 for ; Tue, 20 Nov 2018 18:35:20 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6F5812AC58 for ; Tue, 20 Nov 2018 18:35:20 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 63E992AC5A; Tue, 20 Nov 2018 18:35:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 1601C2AC58 for ; Tue, 20 Nov 2018 18:35:20 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9E2146E430; Tue, 20 Nov 2018 18:35:01 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 76B346E417; Tue, 20 Nov 2018 18:34:59 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Nov 2018 10:34:58 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,258,1539673200"; d="scan'208";a="251262944" Received: from labuser-z97x-ud5h.jf.intel.com ([10.54.75.151]) by orsmga004.jf.intel.com with ESMTP; 20 Nov 2018 10:34:57 -0800 From: Manasi Navare To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH v10 00/23] Respin of remaining DSC + FEC patches Date: Tue, 20 Nov 2018 10:37:13 -0800 Message-Id: <20181120183736.28054-1-manasi.d.navare@intel.com> X-Mailer: git-send-email 2.19.1 MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Manasi Navare Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP This patch series addresses review comments from previous series posted: https://patchwork.freedesktop.org/series/52461/ Anusha Srivatsa (4): i915/dp/fec: Add fec_enable to the crtc state. drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION i915/dp/fec: Configure the Forward Error Correction bits. drm/i915/fec: Disable FEC state. Gaurav K Singh (3): drm/i915/dsc: Define & Compute VESA DSC params drm/i915/dsc: Compute Rate Control parameters for DSC drm/i915/dp: Enable/Disable DSC in DP Sink Manasi Navare (15): drm/dsc: Modify DRM helper to return complete DSC color depth capabilities drm/dsc: Define Display Stream Compression PPS infoframe drm/dsc: Define VESA Display Stream Compression Capabilities drm/dsc: Add helpers for DSC picture parameter set infoframes drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants drm/i915/dp: Add DSC params and DSC config to intel_crtc_state drm/i915/dp: Compute DSC pipe config in atomic check drm/i915/dp: Do not enable PSR2 if DSC is enabled drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes drm/i915/dp: Configure Display stream splitter registers during DSC enable drm/i915/dp: Disable DSC in source by disabling DSS CTL bits drm/i915/dsc: Enable and disable appropriate power wells for VDSC Srivatsa, Anusha (1): drm/dsc: Define Rate Control values that do not change over configurations Documentation/gpu/drm-kms-helpers.rst | 12 + drivers/gpu/drm/Makefile | 2 +- drivers/gpu/drm/drm_dp_helper.c | 14 +- drivers/gpu/drm/drm_dsc.c | 228 +++++ drivers/gpu/drm/i915/Makefile | 3 +- drivers/gpu/drm/i915/i915_drv.h | 4 + drivers/gpu/drm/i915/i915_reg.h | 3 + drivers/gpu/drm/i915/intel_ddi.c | 75 +- drivers/gpu/drm/i915/intel_display.c | 4 +- drivers/gpu/drm/i915/intel_display.h | 3 +- drivers/gpu/drm/i915/intel_dp.c | 233 ++++- drivers/gpu/drm/i915/intel_drv.h | 21 + drivers/gpu/drm/i915/intel_hdmi.c | 21 +- drivers/gpu/drm/i915/intel_psr.c | 14 + drivers/gpu/drm/i915/intel_runtime_pm.c | 4 +- drivers/gpu/drm/i915/intel_vdsc.c | 1088 +++++++++++++++++++++++ include/drm/drm_dp_helper.h | 6 +- include/drm/drm_dsc.h | 485 ++++++++++ 18 files changed, 2179 insertions(+), 41 deletions(-) create mode 100644 drivers/gpu/drm/drm_dsc.c create mode 100644 drivers/gpu/drm/i915/intel_vdsc.c create mode 100644 include/drm/drm_dsc.h