From patchwork Thu Sep 19 06:57:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jitao Shi X-Patchwork-Id: 11151677 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BA480112B for ; Thu, 19 Sep 2019 06:58:28 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A253B21848 for ; Thu, 19 Sep 2019 06:58:28 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A253B21848 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 27B4D6F77A; Thu, 19 Sep 2019 06:58:26 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mailgw02.mediatek.com (unknown [1.203.163.81]) by gabe.freedesktop.org (Postfix) with ESMTP id 07CDF6F76E for ; Thu, 19 Sep 2019 06:58:23 +0000 (UTC) X-UUID: 2e5c475d449e48829af3e5306207e18a-20190919 X-UUID: 2e5c475d449e48829af3e5306207e18a-20190919 Received: from mtkcas34.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 411866299; Thu, 19 Sep 2019 14:58:14 +0800 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by MTKMBS33N2.mediatek.inc (172.27.4.76) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 19 Sep 2019 14:58:10 +0800 Received: from mszsdclx1018.gcn.mediatek.inc (172.27.4.253) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 19 Sep 2019 14:58:09 +0800 From: Jitao Shi To: CK Hu , David Airlie , Daniel Vetter , Subject: [PATCH v7 0/9] Support dsi for mt8183 Date: Thu, 19 Sep 2019 14:57:57 +0800 Message-ID: <20190919065806.111016-1-jitao.shi@mediatek.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 X-TM-SNTS-SMTP: D62ABCF55B85138BF60811A1B649122AB907DE58EFCC9D9BE31F9CBE4AB89AD62000:8 X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jitao Shi , srv_heupstream@mediatek.com, stonea168@163.com, cawa.cheng@mediatek.com, sj.huang@mediatek.com, linux-mediatek@lists.infradead.org, Matthias Brugger , yingjoe.chen@mediatek.com, eddie.huang@mediatek.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Changes since v6: - add dphy reset to avoid dphy fifo error after lines number setting - separate dsi cmd reg setting from "fixes CMDQ reg address of mt8173 is different with mt2701" Changes since v5: - fine tune dphy timing. Changes since v4: - move mipi_dsi_host_unregiter() to .remove() - fine tune add frame size control coding style - change the data type of data_rate as u32, and add DIV_ROUND_UP_ULL - use div_u64 when 8000000000ULL / dsi->data_rate. Changes since v3 - add one more 'tab' for bitwise define. - add Tested-by: Ryan Case and Reviewed-by: CK Hu . - remove compare da_hs_zero to da_hs_prepare. Changes since v2: - change the video timing calc method - fine the dsi and mipitx init sequence - fine tune commit msg Changes since v1: - separate frame size and reg commit control independent patches. - fix some return values in probe - remove DSI_CMDW0 in "CMDQ reg address of mt8173 is different with mt2701" Jitao Shi (9): drm/mediatek: move mipi_dsi_host_register to probe drm/mediatek: fixes CMDQ reg address of mt8173 is different with mt2701 drm/mediatek: replace writeb() with mtk_dsi_mask() drm/mediatek: add dsi reg commit disable control drm/mediatek: add frame size control drm/mediatek: add mt8183 dsi driver support drm/mediatek: change the dsi phytiming calculate method drm: mediatek: adjust dsi and mipi_tx probe sequence drm/mediatek: add dphy reset after setting lanes number drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 +- drivers/gpu/drm/mediatek/mtk_dsi.c | 233 ++++++++++++++++++------- 2 files changed, 170 insertions(+), 65 deletions(-)