From patchwork Thu Jul 22 09:26:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?SmFzb24tSkggTGluICjmnpfnnb/npaUp?= X-Patchwork-Id: 12393555 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8AF7EC63793 for ; Thu, 22 Jul 2021 09:26:34 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 299DC6120C for ; Thu, 22 Jul 2021 09:26:34 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 299DC6120C Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B22156E993; Thu, 22 Jul 2021 09:26:33 +0000 (UTC) Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by gabe.freedesktop.org (Postfix) with ESMTPS id B26566E993 for ; Thu, 22 Jul 2021 09:26:32 +0000 (UTC) X-UUID: 54fab4c9e1eb4f87a70ac6f3b96f68dc-20210722 X-UUID: 54fab4c9e1eb4f87a70ac6f3b96f68dc-20210722 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1540554075; Thu, 22 Jul 2021 17:26:28 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs02n2.mediatek.inc (172.21.101.101) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 22 Jul 2021 17:26:27 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 22 Jul 2021 17:26:27 +0800 From: jason-jh.lin To: Rob Herring , Chun-Kuang Hu , Philipp Zabel Subject: [PATCH v1 0/5] add mt8195 SoC DRM binding Date: Thu, 22 Jul 2021 17:26:19 +0800 Message-ID: <20210722092624.14401-1-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Jitao shi , fshao@chromium.org, David Airlie , "jason-jh . lin" , singo.chang@mediatek.com, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Fabien Parent , nancy.lin@mediatek.com, linux-mediatek@lists.infradead.org, Matthias Brugger , linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add mt8195 SoC DRM binding 1. Due to the 2 display hardware path in mt8195 SoC, we need to add vdosys0 and vdosys1 into mmsys binding document. 2. DSC and MERGE is used in vdosys0, so we need to add DSC binding file and additional MERGE description into original disp binding document. jason-jh.lin (5): dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding dt-bindings: mediatek: display: Change format to yaml dt-bindings: mediatek: display: add MERGE additional description dt-bindings: mediatek: add mediatek,dsc.yaml for mt8195 SoC binding dt-bindings: mediatek: display: add mt8195 SoC binding .../bindings/arm/mediatek/mediatek,mmsys.yaml | 2 + .../display/mediatek/mediatek,disp.txt | 219 --------- .../display/mediatek/mediatek,disp.yaml | 464 ++++++++++++++++++ .../display/mediatek/mediatek,dsc.yaml | 73 +++ 4 files changed, 539 insertions(+), 219 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml