From patchwork Wed Sep 15 22:31:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jitao Shi X-Patchwork-Id: 12497603 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,MIME_BASE64_TEXT,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47A0AC433EF for ; Wed, 15 Sep 2021 22:36:41 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 07F0F6023D for ; Wed, 15 Sep 2021 22:36:41 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 07F0F6023D Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3D72989F0B; Wed, 15 Sep 2021 22:36:40 +0000 (UTC) X-Greylist: delayed 301 seconds by postgrey-1.36 at gabe; Wed, 15 Sep 2021 22:36:38 UTC Received: from mailgw01.mediatek.com (unknown [1.203.163.78]) by gabe.freedesktop.org (Postfix) with ESMTP id 810AA89EB7 for ; Wed, 15 Sep 2021 22:36:38 +0000 (UTC) X-UUID: f3196c0ae63f4b62806365649775f9df-20210916 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=wd4AHgRylyyah26OepnTFpZldLYrIb0DmjPk2ihhdak=; b=TIuaieUwd0oD14bV/ChZMbED+oJn67CUmwXf1hyJlun23wR0g+BfUpiTdv8wgQQrBLzv9DSQduD9sMmNCWJW0S0C3JzJCQ1yNe671zxOWbIFC7DyaA6UNf9ShelJEuJFfghEgP25uQ4X97CwR9LrnRW8Joy6FmqXYmC5cEJEnBw=; X-UUID: f3196c0ae63f4b62806365649775f9df-20210916 Received: from mtkcas32.mediatek.inc [(172.27.7.253)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 985539400; Thu, 16 Sep 2021 06:31:32 +0800 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by MTKMBS33N2.mediatek.inc (172.27.4.76) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 16 Sep 2021 06:31:25 +0800 Received: from mszsdclx1018.gcn.mediatek.inc (10.16.6.18) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 16 Sep 2021 06:31:24 +0800 From: Jitao Shi To: Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , Daniel Vetter , David Airlie , , CC: , , , , , , , Jitao Shi Subject: [PATCH v7 0/3] force hsa hbp hfp packets multiple of lanenum to avoid screen shift Date: Thu, 16 Sep 2021 06:31:14 +0800 Message-ID: <20210915223117.7857-1-jitao.shi@mediatek.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-TM-SNTS-SMTP: 101387587980953D686CCAE49E93230E7C3CB646B0F487D43AC92405D5FD9DC02000:8 X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Changes since v6: - Add "bool hs_packet_end_aligned" in "struct mipi_dsi_device" to control the dsi aligned. - Config the "hs_packet_end_aligned" in ANX7725 .attach(). Changes since v5: - Search the anx7625 compatible as flag to control dsi output aligned. Changes since v4: - Move "dt-bindings: drm/bridge: anx7625: add force_dsi_end_without_null" before "drm/mediatek: force hsa hbp hfp packets multiple of lanenum to avoid". - Retitle "dt-bindings: drm/bridge: anx7625: add force_dsi_end_without_null". Jitao Shi (3): drm/dsi: transer dsi hs packet aligned drm/mediatek: implment the dsi hs packets aligned drm/bridge: anx7625: config hs packets end aligned to avoid screen shift drivers/gpu/drm/bridge/analogix/anx7625.c | 1 + drivers/gpu/drm/mediatek/mtk_dsi.c | 10 ++++++++++ include/drm/drm_mipi_dsi.h | 2 ++ 3 files changed, 13 insertions(+)