mbox series

[v3,0/8] DG2 accelerated migration/clearing support

Message ID 20211206133140.3166205-1-matthew.auld@intel.com (mailing list archive)
Headers show
Series DG2 accelerated migration/clearing support | expand

Message

Matthew Auld Dec. 6, 2021, 1:31 p.m. UTC 
Enable accelerated moves and clearing on DG2. On such HW we have minimum page
size restrictions when accessing LMEM from the GTT, where we now have to use 64K
GTT pages or larger. With the ppGTT the page-table also has a slightly different
layout from past generations when using the 64K GTT mode(which is still enabled
on via some PDE bit), where it is now compacted down to 32 qword entries. Note
that on discrete the paging structures must also be placed in LMEM, and we need
to able to modify them via the GTT itself(see patch 7), which is one of the
complications here.

The series needs to be applied on top of the DG2 enabling branch:
https://cgit.freedesktop.org/~ramaling/linux/log/?h=dg2_enabling_ww49.3

Matthew Auld (8):
  drm/i915/migrate: don't check the scratch page
  drm/i915/migrate: fix offset calculation
  drm/i915/migrate: fix length calculation
  drm/i915/selftests: handle object rounding
  drm/i915/gtt: allow overriding the pt alignment
  drm/i915/gtt: add xehpsdv_ppgtt_insert_entry
  drm/i915/migrate: add acceleration support for DG2
  drm/i915/migrate: turn on acceleration for DG2

 drivers/gpu/drm/i915/gt/gen8_ppgtt.c       |  50 +++++-
 drivers/gpu/drm/i915/gt/intel_gtt.h        |  10 +-
 drivers/gpu/drm/i915/gt/intel_migrate.c    | 195 ++++++++++++++++-----
 drivers/gpu/drm/i915/gt/intel_ppgtt.c      |  16 +-
 drivers/gpu/drm/i915/gt/selftest_migrate.c |   1 +
 5 files changed, 221 insertions(+), 51 deletions(-)

Comments

Daniel Stone Dec. 6, 2021, 2:49 p.m. UTC | #1 
Hi Matthew,

On Mon, 6 Dec 2021 at 13:32, Matthew Auld <matthew.auld@intel.com> wrote:
> Enable accelerated moves and clearing on DG2. On such HW we have minimum page
> size restrictions when accessing LMEM from the GTT, where we now have to use 64K
> GTT pages or larger. With the ppGTT the page-table also has a slightly different
> layout from past generations when using the 64K GTT mode(which is still enabled
> on via some PDE bit), where it is now compacted down to 32 qword entries. Note
> that on discrete the paging structures must also be placed in LMEM, and we need
> to able to modify them via the GTT itself(see patch 7), which is one of the
> complications here.
>
> The series needs to be applied on top of the DG2 enabling branch:
> https://cgit.freedesktop.org/~ramaling/linux/log/?h=dg2_enabling_ww49.3

What are the changes to the v1/v2?

Cheers,
Daniel
Matthew Auld Dec. 6, 2021, 3:13 p.m. UTC | #2 
On 06/12/2021 14:49, Daniel Stone wrote:
> Hi Matthew,
> 
> On Mon, 6 Dec 2021 at 13:32, Matthew Auld <matthew.auld@intel.com> wrote:
>> Enable accelerated moves and clearing on DG2. On such HW we have minimum page
>> size restrictions when accessing LMEM from the GTT, where we now have to use 64K
>> GTT pages or larger. With the ppGTT the page-table also has a slightly different
>> layout from past generations when using the 64K GTT mode(which is still enabled
>> on via some PDE bit), where it is now compacted down to 32 qword entries. Note
>> that on discrete the paging structures must also be placed in LMEM, and we need
>> to able to modify them via the GTT itself(see patch 7), which is one of the
>> complications here.
>>
>> The series needs to be applied on top of the DG2 enabling branch:
>> https://cgit.freedesktop.org/~ramaling/linux/log/?h=dg2_enabling_ww49.3
> 
> What are the changes to the v1/v2?

Yeah, I should have added that somewhere. Sorry.

v2: Add missing cover letter
v3:
- Add some r-b tags
- Drop the GTT_MAPPABLE approach. We can instead simply pass along the 
required size/alignment using alloc_pt().

> 
> Cheers,
> Daniel
>