From patchwork Thu Sep 15 16:18:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Jason-JH.Lin" X-Patchwork-Id: 12977612 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A24C4C6FA89 for ; Thu, 15 Sep 2022 16:18:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DDF3110EB5F; Thu, 15 Sep 2022 16:18:53 +0000 (UTC) Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3BD1E10EB5C for ; Thu, 15 Sep 2022 16:18:25 +0000 (UTC) X-UUID: 839ea7916bba456db7a9a37ad0a48d8c-20220916 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=DAWVVulcpKwL+ZYTIARdiSwHJbxhu980TsdhqLcSfSk=; b=K57zQpkuUZFPXqyL2tmjdGqe70m2UuEbg4k0Hc2T+2dVd9ykCj0W19rOEye7kP8C4XfYQKCx0UACuQEyQnh67Zv68K5cYKmC6tTp6RIqMwBoBO+EAMr11JSmyPn2WA5Tz96mXahK0MtAgnUNqyBvSgqc0EJZUStUY424/z79cRY=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11, REQID:f8ab94d8-e6a7-4b43-8892-c888242ae894, IP:0, U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:39a5ff1, CLOUDID:0e3dc57b-ea28-4199-b57e-003c7d60873a, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 839ea7916bba456db7a9a37ad0a48d8c-20220916 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 963899002; Fri, 16 Sep 2022 00:18:20 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Fri, 16 Sep 2022 00:18:18 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Fri, 16 Sep 2022 00:18:18 +0800 From: Jason-JH.Lin To: Matthias Brugger , Chun-Kuang Hu , Rob Herring , "Krzysztof Kozlowski" , AngeloGioacchino Del Regno Subject: [PATCH v2 0/6] Change mmsys compatible for mt8195 mediatek-drm Date: Fri, 16 Sep 2022 00:18:11 +0800 Message-ID: <20220915161817.10307-1-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, "Jason-JH.Lin" , Singo Chang , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Project_Global_Chrome_Upstream_Group@mediatek.com, Rex-BC Chen , Nancy Lin , linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" For previous MediaTek SoCs, such as MT8173, there are 2 display HW pipelines binding to 1 mmsys with the same power domain, the same clock driver and the same mediatek-drm driver. For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding to 2 different power domains, different clock drivers and different mediatek-drm drivers. Moreover, Hardware pipeline of VDOSYS0 has these components: COLOR, CCORR, AAL, GAMMA, DITHER. They are related to the PQ (Picture Quality) and they makes VDOSYS0 supports PQ function while they are not including in VDOSYS1. Hardware pipeline of VDOSYS1 has the component ETHDR (HDR related component). It makes VDOSYS1 supports the HDR function while it's not including in VDOSYS0. To summarize0: Only VDOSYS0 can support PQ adjustment. Only VDOSYS1 can support HDR adjustment. Therefore, we need to separate these two different mmsys hardwares to 2 different compatibles for MT8195. --- Change in v2: 1. Remove Ack tag in the first patch 2. Change the compatible name changing patch to one revert patch and one add vdosys0 support patch. --- Jason-JH.Lin (6): dt-bindings: arm: mediatek: mmsys: change compatible for MT8195 Revert "soc: mediatek: add mtk-mmsys support for mt8195 vdosys0" soc: mediatek: add mtk-mmsys support for mt8195 vdosys0 Revert "drm/mediatek: Add mediatek-drm of vdosys0 support for mt8195" drm/mediatek: add mediatek-drm of vdosys0 support for mt8195 soc: mediatek: remove DDP_DOMPONENT_DITHER from enum .../bindings/arm/mediatek/mediatek,mmsys.yaml | 2 +- drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 128 ++-------------- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 6 - drivers/soc/mediatek/mtk-mmsys.c | 145 ++---------------- drivers/soc/mediatek/mtk-mmsys.h | 6 - include/linux/soc/mediatek/mtk-mmsys.h | 3 +- 7 files changed, 34 insertions(+), 262 deletions(-)