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[83.9.2.151]) by smtp.gmail.com with ESMTPSA id c23-20020ac244b7000000b004db5081e3f7sm505126lfm.46.2023.02.22.13.47.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 13:47:11 -0800 (PST) From: Konrad Dybcio Subject: [PATCH 0/5] OPP and devfreq for all Adrenos Date: Wed, 22 Feb 2023 22:47:09 +0100 Message-Id: <20230222-konrad-longbois-next-v1-0-01021425781b@linaro.org> MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAF2N9mMC/x2N0QrCMAwAf2Xk2cCW4VB/RXxI27gFSyrplMHYv 1t8vIPjdqjiKhVu3Q4uX61arMFw6iAubLOgpsZAPY09EeGrmHPCXGwORSuabCtepjTwdD2PFAl aGrgKBmeLS4vtk3OTb5enbv/X/XEcP343Cs57AAAA To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1677102430; l=2087; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=ocr3jeuvoRq3y9CSWJWmDlXSkvIkpCb9rcZR7Ldt8y0=; b=GnX5hx4k4NEFLxBrvnFkBrpW7jm1Yg1bxr4NqiOJ1CEFH/5VtjvD1XT/pHQKEdLz6RaWIHFdv0a9 l2zbUi+tB7Th6+9ZQ07IS4Xo5xNTXebzV60EY+88yeyROg2CK1qd X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Konrad Dybcio , linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" This series is a combination of [1] and a subset of [2] and some new stuff. With it, devfreq is used on all a2xx-a6xx (including gmu and gmu-wrapper) and all clk_set_rate(core clock) calls are dropped in favour of dev_pm_opp_set_rate, which - drumroll - lets us scale the voltage domain. DT patches making use of that will be sent separately. On top of that, a5xx gets a call to enable icc scaling from the OPP tables. No SoCs implementing a2xx have icc support yet and a3/4xx SoCs have separate logic for that, which will be updated at a later time. Getting this in for 6.4 early would be appreciated, as that would allow for getting GMU wrapper GPUs up (without VDD&icc scaling they can only run at lower freqs, which is.. ehhh..) Changes: - a3xx busy: use the _1 counter as per msm-3.x instead of _0 - a6xx-series-opp: basically rewrite, ensure compat with all gens - a2/4xx busy: new patch - a5xx icc: new patch [1] https://lore.kernel.org/linux-arm-msm/20230130093809.2079314-1-konrad.dybcio@linaro.org/ [2] https://lore.kernel.org/linux-arm-msm/20230214173145.2482651-1-konrad.dybcio@linaro.org/ Signed-off-by: Konrad Dybcio --- Konrad Dybcio (5): drm/msm/adreno: Use OPP for every GPU generation drm/msm/a2xx: Implement .gpu_busy drm/msm/a3xx: Implement .gpu_busy drm/msm/a4xx: Implement .gpu_busy drm/msm/a5xx: Enable optional icc voting from OPP tables drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 28 ++++++++++ drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 11 ++++ drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 11 ++++ drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 ++ drivers/gpu/drm/msm/adreno/adreno_gpu.c | 94 +++++++++++++++------------------ drivers/gpu/drm/msm/msm_gpu.c | 4 +- drivers/gpu/drm/msm/msm_gpu_devfreq.c | 2 +- 7 files changed, 99 insertions(+), 55 deletions(-) --- base-commit: f4ed0868966d96203fee6f2782508746ded2ce3f change-id: 20230222-konrad-longbois-next-86d1a69532c2 Best regards,