From patchwork Mon Jun 12 09:01:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 13275843 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B0AADC7EE23 for ; Mon, 12 Jun 2023 09:02:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id ACB9410E0C2; Mon, 12 Jun 2023 09:02:05 +0000 (UTC) Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by gabe.freedesktop.org (Postfix) with ESMTPS id BE00110E09E for ; Mon, 12 Jun 2023 09:02:04 +0000 (UTC) Received: from IcarusMOD.eternityproject.eu (unknown [IPv6:2001:b07:2ed:14ed:c5f8:7372:f042:90a2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id BB56866056AA; Mon, 12 Jun 2023 10:02:01 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1686560522; bh=7oxMNTbloKgt3ufFjwheFe+Sm5DenM+mJvuQ6Eo92T4=; h=From:To:Cc:Subject:Date:From; b=jODar/9ILGQ61B8Y3oo3ExipDRt7J6vpfQGjKl4iQveBivCoWoHFXtkG9bypmTq0A PBXw3GetSREvMKFTU71vM8qInMFNRtHbrHXMDVSGc6X8Gt2wKQ/0exnaKqj3zRsgvl 2Buc+CI3FVx4Xn7wGfsbKYRFwFk34Py26e31KSZYkzScRSCtwyV7SPUCB+npK4ZAyF zQMhoglF8g/vMb2teAz8L6QRnGgQIQhJ++wurGOk2xLOy4j5FRgWreE8kt5ENDAtTX dgpCntX4btMwiNy/qQz+WiSYybgAYjrShkbHZpns9LvNX5Wd9A4ux4JyV90eaa4ui/ Ohsy4AsphxLqA== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Subject: [PATCH v6 00/11] MediaTek DDP GAMMA - 12-bit LUT support Date: Mon, 12 Jun 2023 11:01:46 +0200 Message-Id: <20230612090157.68205-1-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.40.1 MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, wenst@chromium.org, matthias.bgg@gmail.com, kernel@collabora.com, linux-arm-kernel@lists.infradead.org, angelogioacchino.delregno@collabora.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Changes in v6: - Fixed smatch warning in patch 11/11, ref.: https://lore.kernel.org/all/202306101458.lRXHEE0Z-lkp@intel.com/ Changes in v5: - Removed incorrect comment on default LUT size and bits - Removed useless check for num_lut_banks - Added comment about CMDQ implementation on patch 5 - Evaluated passing lut size/bits from AAL, idea discarded as the implementation would be rather tricky while bringing no benefits. Changes in v4: - Fixed assignment typo appeared in v3 Changes in v3: - Fixed issues due to variables renaming during cleanup (oops) - This is actually the right series, since v2 was taken from the wrong kernel tree.... :-) Changes in v2: - Added explicit inclusion of linux/bitfield.h in patch [06/11] This series adds support for GAMMA IP requiring and/or supporting a 12-bits LUT using a slightly different register layout and programming sequence for multiple LUT banks: this IP version is currently found on a number of SoCs, not only including the Chromebook/IoT oriented Kompanio 1200/1380 MT8195/MT8195T, but also Smartphone chips such as the Dimensity 9200 (MT6985) and others. This series was tested on MT8195, MT8192, MT8173, MT6795: * MT6795, MT8192, MT8173: No regression, works fine. * MT8195: Color correction is finally working! AngeloGioacchino Del Regno (10): drm/mediatek: gamma: Reduce indentation in mtk_gamma_set_common() drm/mediatek: gamma: Support SoC specific LUT size drm/mediatek: gamma: Improve and simplify HW LUT calculation drm/mediatek: gamma: Enable the Gamma LUT table only after programming drm/mediatek: gamma: Use bitfield macros drm/mediatek: gamma: Support specifying number of bits per LUT component drm/mediatek: gamma: Support multi-bank gamma LUT drm/mediatek: gamma: Add support for 12-bit LUT and MT8195 drm/mediatek: gamma: Make sure relay mode is disabled drm/mediatek: gamma: Program gamma LUT type for descending or rising Jason-JH.Lin (1): drm/mediatek: gamma: Adjust mtk_drm_gamma_set_common parameters drivers/gpu/drm/mediatek/mtk_disp_aal.c | 2 +- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 3 +- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 193 ++++++++++++++++---- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 4 +- drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 1 - drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 + drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 9 + 7 files changed, 177 insertions(+), 36 deletions(-)