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[v7,0/3] drm/i915/pxp/mtl: Update gsc-heci cmd submission to align with fw/hw spec

Message ID 20230917211933.1407559-1-alan.previn.teres.alexis@intel.com (mailing list archive)
Headers show
Series drm/i915/pxp/mtl: Update gsc-heci cmd submission to align with fw/hw spec | expand

Message

Alan Previn Sept. 17, 2023, 9:19 p.m. UTC 
For MTL, update the GSC-HECI packet size and the max firmware
response timeout to match internal fw specs. Enforce setting
run-alone bit in LRC for protected contexts.

Changes from prio revs:
   v6: - fix build error with PXP config (Alan)
   v5: - PAGE_ALIGN typo fix (Alan).
       - Use macro for runalone bit (Vivaik)
       - Spec alignment with system overhead,
         increase fw timeout to 500ms (Alan)
   v4: - PAGE_ALIGN the max heci packet size (Alan).
   v3: - Patch #1. Only start counting the request completion
         timeout from after the request has started (Daniele).
   v2: - Patch #3: fix sparse warning reported by kernel test robot.
   v1: - N/A (Re-test)

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>

Alan Previn (3):
  drm/i915/pxp/mtl: Update pxp-firmware response timeout
  drm/i915/pxp/mtl: Update pxp-firmware packet size
  drm/i915/lrc: User PXP contexts requires runalone bit in lrc

 drivers/gpu/drm/i915/gt/intel_engine_regs.h   |  1 +
 drivers/gpu/drm/i915/gt/intel_lrc.c           | 23 +++++++++++++++++++
 .../i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c | 20 ++++++++++++++--
 .../i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h |  6 +++++
 .../drm/i915/pxp/intel_pxp_cmd_interface_43.h |  4 ++--
 drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c    |  2 +-
 drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h    | 10 ++++----
 7 files changed, 55 insertions(+), 11 deletions(-)


base-commit: dc4cd6e4e53d46211952fe7c0e408fce3e212993