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Tue, 23 Jan 2024 18:54:03 -0800 Received: from xsjanatoliy50.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.34 via Frontend Transport; Tue, 23 Jan 2024 20:54:03 -0600 From: Anatoliy Klymenko To: , , , , , , , , , Subject: [PATCH v3 0/5] Fixing live video input in ZynqMP DPSUB Date: Tue, 23 Jan 2024 18:53:57 -0800 Message-ID: <20240124025402.373620-1-anatoliy.klymenko@amd.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002636C:EE_|MW4PR12MB6849:EE_ X-MS-Office365-Filtering-Correlation-Id: b12f5e21-0d49-45ef-32e7-08dc1c87ba4f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: hk/PElpcSKMDOloX9JlRbE+VKQsvZCYmoHBeNmIDs7HE2EswSTB3kMgx/be8s1G0r8Aes70c6ffjDEk6riXc0eFkhzYE/E9RfoXJy7xH2vLMeoPJAMZ6Q0If3qSvqWa5lBkUsBsA07cnzUQq3aVqPari0+vctqp8AkZDSneNZ6W9k4D/HHs1EAqMDObXSFSia65gpbMewOEvyE/mWJeUgP3Qn+D/8B7RBfAAxBraF39G/jLsi/mIH6U1s+UDJCeNVPDiAWt4rVTacYJf5wutiUfbOYGlcTvZj1ILUNPw+SI7nyPMK0HzBOotf7CvRpNSpWEmUtpB/rPJcSLBmt1vK1lxSBHwXsS/RfXj1kf8YtjVW48eR9WTHJRSgukmdowkep1+ilwWgLDpEr5GhSEWl0ndtboYMJdmIRrJAwbjq+YmTJEm5dMONXQA6/7Yf7giO2NXq3Kg2WFe2Qw69lUGgRpIU1Z/2akEEbabJHLU/NdfU6FvVsdB78tYqMJNLYFdex8NK2HIIQjnrRLvSZ+C9gGL0sFy889hmUk89JmxtFWQt55ZtIwSA5uVNj/3nMHVQJ9tePRb37bkU/5SeOj6fxuGNfBn/mQyslV7p98eajj9RvXMFtBEpxK9EHbkWCpu1J2hNHfLzpOCcPYCNRMn4gp42mQZByKXUXXaO1YjqDZAKxhI+rrjB8ndkRo/6LLRy4JBUGhINW/sCUc7d5zx/YjeEWPDjyP4aMqkkaGpRc8HMIQNCCp4WBJhgpmn841Wge9rEURNIJluL63J1fZVpacNji6NSBFhDz/ou72QrSLvQdhIeNhCTmFBW8wvM34LLvgqRQUR/A0KabNNRQrVArBEFHvGDkzAmzlqYH2inl36WU3OktkizrEUrQ4XnCB8DtHBV5SubZq7DW4mLmFMTA== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB03.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(4636009)(39860400002)(376002)(136003)(346002)(396003)(230273577357003)(230173577357003)(230922051799003)(64100799003)(451199024)(1800799012)(186009)(82310400011)(46966006)(40470700004)(36840700001)(82740400003)(316002)(6666004)(921011)(8936002)(5660300002)(44832011)(86362001)(2906002)(81166007)(70586007)(41300700001)(110136005)(36756003)(356005)(70206006)(966005)(8676002)(478600001)(40460700003)(40480700001)(426003)(36860700001)(336012)(26005)(1076003)(83380400001)(2616005)(47076005)(2101003)(36900700001)(83996005); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jan 2024 02:54:05.1058 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b12f5e21-0d49-45ef-32e7-08dc1c87ba4f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002636C.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6849 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add few missing pieces to support ZynqMP DPSUB live video in mode. ZynqMP DPSUB supports 2 modes of operations in regard to video data input. In the first mode, DPSUB uses DMA engine to pull video data from memory buffers. To support this the driver implements CRTC and DRM bridge representing DP encoder. In the second mode, DPSUB acquires video data pushed from FPGA and passes it downstream to DP output. This mode of operation is modeled in the driver as a DRM bridge that should be attached to some external CRTC. Patches 1/5,2/5,3/5,4/5 are minor fixes. DPSUB requires input live video format to be configured. Patch 5/5: The DP Subsystem requires the input live video format to be configured. In this patch, we are assuming that the CRTC's bus format is fixed (typical for FPGA CRTC) and comes from the device tree. This is a proposed solution, as there is no API to query CRTC output bus format or negotiate it in any other way. Changes in v2: - Address reviewers' comments: - More elaborate and consistent comments / commit messages - Fix includes' order - Replace of_property_read_u32_index() with of_property_read_u32() Changes in v3: - Split patch #3 into 3) moving status register clear immediately after read; 4) masking status against interrupts' mask Link to v1: https://lore.kernel.org/all/20240112234222.913138-1-anatoliy.klymenko@amd.com/ Link to v2: https://lore.kernel.org/all/20240119055437.2549149-1-anatoliy.klymenko@amd.com/ Anatoliy Klymenko (5): drm: xlnx: zynqmp_dpsub: Make drm bridge discoverable drm: xlnx: zynqmp_dpsub: Fix timing for live mode drm: xlnx: zynqmp_dpsub: Clear status register ASAP drm: xlnx: zynqmp_dpsub: Filter interrupts against mask drm: xlnx: zynqmp_dpsub: Set live video in format drivers/gpu/drm/xlnx/zynqmp_disp.c | 111 +++++++++++++++++++++--- drivers/gpu/drm/xlnx/zynqmp_disp.h | 3 +- drivers/gpu/drm/xlnx/zynqmp_disp_regs.h | 8 +- drivers/gpu/drm/xlnx/zynqmp_dp.c | 16 +++- drivers/gpu/drm/xlnx/zynqmp_kms.c | 2 +- 5 files changed, 119 insertions(+), 21 deletions(-)